[dpdk-dev,v4,1/2] eal/tile: add rte_vect.h and enable CONFIG_RTE_LIBRTE_LPM
Commit Message
rte_vect.h was missing earlier thus LPM was disabled and l3fwd is
not able to compile. This commit implements the vector api and
enable LPM in the tilegx configuration by default.
Signed-off-by: Liming Sun <lsun@ezchip.com>
Acked-by: Zhigang Lu <zlu@ezchip.com>
---
config/defconfig_tile-tilegx-linuxapp-gcc | 2 +-
lib/librte_eal/common/include/arch/tile/rte_vect.h | 93 ++++++++++++++++++++++
2 files changed, 94 insertions(+), 1 deletion(-)
create mode 100644 lib/librte_eal/common/include/arch/tile/rte_vect.h
Comments
2016-02-09 23:04, Liming Sun:
> rte_vect.h was missing earlier thus LPM was disabled and l3fwd is
> not able to compile. This commit implements the vector api and
> enable LPM in the tilegx configuration by default.
>
> Signed-off-by: Liming Sun <lsun@ezchip.com>
> Acked-by: Zhigang Lu <zlu@ezchip.com>
[...]
> # This following libraries are not available on the tile architecture.
> # So they're turned off.
> -CONFIG_RTE_LIBRTE_LPM=n
> +CONFIG_RTE_LIBRTE_LPM=y
You just have to remove the disabling line.
> +typedef union rte_xmm {
> + __m128i x;
> + uint32_t u32[XMM_SIZE / sizeof(uint32_t)];
> + uint64_t u64[XMM_SIZE / sizeof(uint64_t)];
> +} rte_xmm_t;
Why do you mimic SSE?
> +/* Shifts right the 4 32-bit integers by count bits with zeros. */
> +#define _mm_srli_epi32(v, cnt) ({ \
> + rte_xmm_t m; \
> + m.u64[0] = __insn_v4shru(((rte_xmm_t*)&(v))->u64[0], cnt); \
> + m.u64[1] = __insn_v4shru(((rte_xmm_t*)&(v))->u64[1], cnt); \
> + (m.x); \
> +})
Please check the work in progress to have arch-specific implementation
of rte_lpm_lookupx4():
http://dpdk.org/dev/patchwork/patch/10478/
Any news? a v5 could be part of the RC2.
2016-03-08 20:59, Thomas Monjalon:
> 2016-02-09 23:04, Liming Sun:
> > rte_vect.h was missing earlier thus LPM was disabled and l3fwd is
> > not able to compile. This commit implements the vector api and
> > enable LPM in the tilegx configuration by default.
> >
> > Signed-off-by: Liming Sun <lsun@ezchip.com>
> > Acked-by: Zhigang Lu <zlu@ezchip.com>
> [...]
> > # This following libraries are not available on the tile architecture.
> > # So they're turned off.
> > -CONFIG_RTE_LIBRTE_LPM=n
> > +CONFIG_RTE_LIBRTE_LPM=y
>
> You just have to remove the disabling line.
>
> > +typedef union rte_xmm {
> > + __m128i x;
> > + uint32_t u32[XMM_SIZE / sizeof(uint32_t)];
> > + uint64_t u64[XMM_SIZE / sizeof(uint64_t)];
> > +} rte_xmm_t;
>
> Why do you mimic SSE?
>
> > +/* Shifts right the 4 32-bit integers by count bits with zeros. */
> > +#define _mm_srli_epi32(v, cnt) ({ \
> > + rte_xmm_t m; \
> > + m.u64[0] = __insn_v4shru(((rte_xmm_t*)&(v))->u64[0], cnt); \
> > + m.u64[1] = __insn_v4shru(((rte_xmm_t*)&(v))->u64[1], cnt); \
> > + (m.x); \
> > +})
>
> Please check the work in progress to have arch-specific implementation
> of rte_lpm_lookupx4():
> http://dpdk.org/dev/patchwork/patch/10478/
@@ -64,7 +64,7 @@ CONFIG_RTE_LIBRTE_ENIC_PMD=n
# This following libraries are not available on the tile architecture.
# So they're turned off.
-CONFIG_RTE_LIBRTE_LPM=n
+CONFIG_RTE_LIBRTE_LPM=y
CONFIG_RTE_LIBRTE_ACL=n
CONFIG_RTE_LIBRTE_SCHED=n
CONFIG_RTE_LIBRTE_PORT=n
new file mode 100644
@@ -0,0 +1,93 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright (C) EZchip Semiconductor Ltd. 2016.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of EZchip Semiconductor nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#ifndef _RTE_VECT_H_
+#define _RTE_VECT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef __int128 __m128i;
+
+#define XMM_SIZE sizeof(__m128i)
+#define XMM_MASK (XMM_SIZE - 1)
+
+typedef union rte_xmm {
+ __m128i x;
+ uint32_t u32[XMM_SIZE / sizeof(uint32_t)];
+ uint64_t u64[XMM_SIZE / sizeof(uint64_t)];
+} rte_xmm_t;
+
+/* Extracts the low order 64-bit integer. */
+#define _mm_cvtsi128_si64(a) ((rte_xmm_t*)&a)->u64[0]
+
+/* Sets the 2 signed 64-bit integer values. */
+#define _mm_set_epi64x(i1, i0) ({ \
+ rte_xmm_t m; \
+ m.u64[0] = i0; \
+ m.u64[1] = i1; \
+ (m.x); \
+})
+
+/* Sets the 4 signed 32-bit integer values. */
+#define _mm_set_epi32(i3, i2, i1, i0) ({ \
+ rte_xmm_t m; \
+ m.u32[0] = i0; \
+ m.u32[1] = i1; \
+ m.u32[2] = i2; \
+ m.u32[3] = i3; \
+ (m.x); \
+})
+
+/* Shifts right the 4 32-bit integers by count bits with zeros. */
+#define _mm_srli_epi32(v, cnt) ({ \
+ rte_xmm_t m; \
+ m.u64[0] = __insn_v4shru(((rte_xmm_t*)&(v))->u64[0], cnt); \
+ m.u64[1] = __insn_v4shru(((rte_xmm_t*)&(v))->u64[1], cnt); \
+ (m.x); \
+})
+
+/* Shifts the 128-bit value in a right by imm bytes. */
+#define _mm_srli_si128(v, imm) ((v) >> (imm * sizeof(uint8_t)))
+
+/* Bitwise AND of the 128-bit value in a and the 128-bit value in b. */
+#define _mm_and_si128(a, b) ((a) & (b))
+
+/* Loads 128-bit value. */
+#define _mm_loadu_si128(p) (*(p))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_VECT_H_ */