[dpdk-dev,v2] net/mlx5: lift Rx RSS indirection table size limit
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Commit Message
The size of Rx RSS indirection table was limited by 256, but it is not
required anymore for all Mellanox NICs. However, the librte_ether still
limits the size by 512.
Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
---
drivers/net/mlx5/mlx5.c | 5 +++--
drivers/net/mlx5/mlx5_defs.h | 3 ---
2 files changed, 3 insertions(+), 5 deletions(-)
Comments
On Tue, Jan 17, 2017 at 04:39:29PM -0800, Yongseok Koh wrote:
> The size of Rx RSS indirection table was limited by 256, but it is not
> required anymore for all Mellanox NICs. However, the librte_ether still
> limits the size by 512.
>
> Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
> ---
> drivers/net/mlx5/mlx5.c | 5 +++--
> drivers/net/mlx5/mlx5_defs.h | 3 ---
> 2 files changed, 3 insertions(+), 5 deletions(-)
Acked-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
On 1/20/2017 4:57 PM, Adrien Mazarguil wrote:
> On Tue, Jan 17, 2017 at 04:39:29PM -0800, Yongseok Koh wrote:
>> The size of Rx RSS indirection table was limited by 256, but it is not
>> required anymore for all Mellanox NICs. However, the librte_ether still
>> limits the size by 512.
>>
>> Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
>> ---
>> drivers/net/mlx5/mlx5.c | 5 +++--
>> drivers/net/mlx5/mlx5_defs.h | 3 ---
>> 2 files changed, 3 insertions(+), 5 deletions(-)
>
> Acked-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
Applied to dpdk-next-net/master, thanks.
@@ -557,8 +557,9 @@ mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
priv->ind_table_max_size = exp_device_attr.rx_hash_caps.max_rwq_indirection_table_size;
/* Remove this check once DPDK supports larger/variable
* indirection tables. */
- if (priv->ind_table_max_size > (unsigned int)RSS_INDIRECTION_TABLE_SIZE)
- priv->ind_table_max_size = RSS_INDIRECTION_TABLE_SIZE;
+ if (priv->ind_table_max_size >
+ (unsigned int)ETH_RSS_RETA_SIZE_512)
+ priv->ind_table_max_size = ETH_RSS_RETA_SIZE_512;
DEBUG("maximum RX indirection table size is %u",
priv->ind_table_max_size);
priv->hw_vlan_strip = !!(exp_device_attr.wq_vlan_offloads_cap &
@@ -54,9 +54,6 @@
*/
#define MLX5_TX_COMP_THRESH 32
-/* RSS Indirection table size. */
-#define RSS_INDIRECTION_TABLE_SIZE 256
-
/*
* Maximum number of cached Memory Pools (MPs) per TX queue. Each RTE MP
* from which buffers are to be transmitted will have to be mapped by this