diff mbox

[dpdk-dev] config: set cache line as 128B in the generic arm64 config

Message ID 20170426162919.15397-1-jerin.jacob@caviumnetworks.com (mailing list archive)
State Accepted, archived
Delegated to: Thomas Monjalon
Headers

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel-compilation success Compilation OK

Commit Message

Jerin Jacob April 26, 2017, 4:29 p.m. UTC 
  armv8 implementations may have 64B or 128B cache line.
Setting to the maximum available cache line size in generic config to
address minimum DMA alignment across all arm64 implementations.

Increasing the cacheline size has no negative impact to cache invalidation
on systems with a smaller cache line.

The need for the minimum DMA alignment has impact on functional aspects
of the platform so default config should cater the functional aspects.

There is an impact on memory usage with this scheme, but that's not too
important for the single image arm64 distribution use case.

The arm64 linux kernel followed the similar approach for single
arm64 image use case.
http://lxr.free-electrons.com/source/arch/arm64/include/asm/cache.h

Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
---
 config/defconfig_arm64-armv8a-linuxapp-gcc | 5 +++++
 config/defconfig_arm64-dpaa2-linuxapp-gcc  | 1 +
 config/defconfig_arm64-xgene1-linuxapp-gcc | 1 +
 3 files changed, 7 insertions(+)

Comments

Jianbo Liu April 28, 2017, 2:14 a.m. UTC | #1 
On 27 April 2017 at 00:29, Jerin Jacob <jerin.jacob@caviumnetworks.com> wrote:
> armv8 implementations may have 64B or 128B cache line.
> Setting to the maximum available cache line size in generic config to
> address minimum DMA alignment across all arm64 implementations.
>
> Increasing the cacheline size has no negative impact to cache invalidation
> on systems with a smaller cache line.
>
> The need for the minimum DMA alignment has impact on functional aspects
> of the platform so default config should cater the functional aspects.
>
> There is an impact on memory usage with this scheme, but that's not too
> important for the single image arm64 distribution use case.
>
> The arm64 linux kernel followed the similar approach for single
> arm64 image use case.
> http://lxr.free-electrons.com/source/arch/arm64/include/asm/cache.h
>
> Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
> ---
>  config/defconfig_arm64-armv8a-linuxapp-gcc | 5 +++++
>  config/defconfig_arm64-dpaa2-linuxapp-gcc  | 1 +
>  config/defconfig_arm64-xgene1-linuxapp-gcc | 1 +
>  3 files changed, 7 insertions(+)
>
> diff --git a/config/defconfig_arm64-armv8a-linuxapp-gcc b/config/defconfig_arm64-armv8a-linuxapp-gcc
> index 65888cef1..0faa2d3a3 100644
> --- a/config/defconfig_arm64-armv8a-linuxapp-gcc
> +++ b/config/defconfig_arm64-armv8a-linuxapp-gcc
> @@ -42,6 +42,11 @@ CONFIG_RTE_FORCE_INTRINSICS=y
>  CONFIG_RTE_TOOLCHAIN="gcc"
>  CONFIG_RTE_TOOLCHAIN_GCC=y
>
> +#Maximum available cache line size in arm64 implementations. Setting to maximum
> +#available cache line size in generic config to address minimum DMA alignment
> +#across all arm64 implementations.
> +CONFIG_RTE_CACHE_LINE_SIZE=128
> +
>  CONFIG_RTE_EAL_IGB_UIO=n
>
>  CONFIG_RTE_LIBRTE_FM10K_PMD=n
> diff --git a/config/defconfig_arm64-dpaa2-linuxapp-gcc b/config/defconfig_arm64-dpaa2-linuxapp-gcc
> index 010cb8092..314a0eceb 100644
> --- a/config/defconfig_arm64-dpaa2-linuxapp-gcc
> +++ b/config/defconfig_arm64-dpaa2-linuxapp-gcc
> @@ -41,6 +41,7 @@ CONFIG_RTE_ARCH_ARM_TUNE="cortex-a57+fp+simd"
>  #
>  CONFIG_RTE_MAX_LCORE=8
>  CONFIG_RTE_MAX_NUMA_NODES=1
> +CONFIG_RTE_CACHE_LINE_SIZE=64
>
>  CONFIG_RTE_PKTMBUF_HEADROOM=256
>
> diff --git a/config/defconfig_arm64-xgene1-linuxapp-gcc b/config/defconfig_arm64-xgene1-linuxapp-gcc
> index f096166b7..d8e544728 100644
> --- a/config/defconfig_arm64-xgene1-linuxapp-gcc
> +++ b/config/defconfig_arm64-xgene1-linuxapp-gcc
> @@ -32,3 +32,4 @@
>  #include "defconfig_arm64-armv8a-linuxapp-gcc"
>
>  CONFIG_RTE_MACHINE="xgene1"
> +CONFIG_RTE_CACHE_LINE_SIZE=64
> --

Acked-by: Jianbo Liu <jianbo.liu@linaro.org>
Santosh Shukla April 28, 2017, 3:59 a.m. UTC | #2 
Hi Jerin,

On Wednesday 26 April 2017 09:59 PM, Jerin Jacob wrote:

> armv8 implementations may have 64B or 128B cache line.
> Setting to the maximum available cache line size in generic config to
> address minimum DMA alignment across all arm64 implementations.
>
> Increasing the cacheline size has no negative impact to cache invalidation
> on systems with a smaller cache line.
>
> The need for the minimum DMA alignment has impact on functional aspects
> of the platform so default config should cater the functional aspects.
>
> There is an impact on memory usage with this scheme, but that's not too
> important for the single image arm64 distribution use case.
>
> The arm64 linux kernel followed the similar approach for single
> arm64 image use case.
> http://lxr.free-electrons.com/source/arch/arm64/include/asm/cache.h
>
> Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
> ---
>  config/defconfig_arm64-armv8a-linuxapp-gcc | 5 +++++
>  config/defconfig_arm64-dpaa2-linuxapp-gcc  | 1 +
>  config/defconfig_arm64-xgene1-linuxapp-gcc | 1 +
>  3 files changed, 7 insertions(+)
>
> diff --git a/config/defconfig_arm64-armv8a-linuxapp-gcc b/config/defconfig_arm64-armv8a-linuxapp-gcc
> index 65888cef1..0faa2d3a3 100644
> --- a/config/defconfig_arm64-armv8a-linuxapp-gcc
> +++ b/config/defconfig_arm64-armv8a-linuxapp-gcc
> @@ -42,6 +42,11 @@ CONFIG_RTE_FORCE_INTRINSICS=y
>  CONFIG_RTE_TOOLCHAIN="gcc"
>  CONFIG_RTE_TOOLCHAIN_GCC=y
>  
> +#Maximum available cache line size in arm64 implementations. Setting to maximum
> +#available cache line size in generic config to address minimum DMA alignment
> +#across all arm64 implementations.
> +CONFIG_RTE_CACHE_LINE_SIZE=128
> +
>  CONFIG_RTE_EAL_IGB_UIO=n
>  
>  CONFIG_RTE_LIBRTE_FM10K_PMD=n
> diff --git a/config/defconfig_arm64-dpaa2-linuxapp-gcc b/config/defconfig_arm64-dpaa2-linuxapp-gcc
> index 010cb8092..314a0eceb 100644
> --- a/config/defconfig_arm64-dpaa2-linuxapp-gcc
> +++ b/config/defconfig_arm64-dpaa2-linuxapp-gcc
> @@ -41,6 +41,7 @@ CONFIG_RTE_ARCH_ARM_TUNE="cortex-a57+fp+simd"
>  #
>  CONFIG_RTE_MAX_LCORE=8
>  CONFIG_RTE_MAX_NUMA_NODES=1
> +CONFIG_RTE_CACHE_LINE_SIZE=64
>  
>  CONFIG_RTE_PKTMBUF_HEADROOM=256
>  
> diff --git a/config/defconfig_arm64-xgene1-linuxapp-gcc b/config/defconfig_arm64-xgene1-linuxapp-gcc
> index f096166b7..d8e544728 100644
> --- a/config/defconfig_arm64-xgene1-linuxapp-gcc
> +++ b/config/defconfig_arm64-xgene1-linuxapp-gcc
> @@ -32,3 +32,4 @@
>  #include "defconfig_arm64-armv8a-linuxapp-gcc"
>  
>  CONFIG_RTE_MACHINE="xgene1"
> +CONFIG_RTE_CACHE_LINE_SIZE=64

Acked-by : Santosh Shukla <santosh.shukla@caviumnetworks.com>

Thanks,!
Jerin Jacob April 28, 2017, 5:03 a.m. UTC | #3 
-----Original Message-----
> Date: Fri, 28 Apr 2017 10:14:11 +0800
> From: Jianbo Liu <jianbo.liu@linaro.org>
> To: Jerin Jacob <jerin.jacob@caviumnetworks.com>
> Cc: dev@dpdk.org, thomas@monjalon.net, Hemant Agrawal
>  <hemant.agrawal@nxp.com>, christian.ehrhardt@canonical.com
> Subject: Re: [dpdk-dev] [PATCH] config: set cache line as 128B in the
>  generic arm64 config
> 
> On 27 April 2017 at 00:29, Jerin Jacob <jerin.jacob@caviumnetworks.com> wrote:
> > armv8 implementations may have 64B or 128B cache line.
> > Setting to the maximum available cache line size in generic config to
> > address minimum DMA alignment across all arm64 implementations.
> >
> > Increasing the cacheline size has no negative impact to cache invalidation
> > on systems with a smaller cache line.
> >
> > The need for the minimum DMA alignment has impact on functional aspects
> > of the platform so default config should cater the functional aspects.
> >
> > There is an impact on memory usage with this scheme, but that's not too
> > important for the single image arm64 distribution use case.
> >
> > The arm64 linux kernel followed the similar approach for single
> > arm64 image use case.
> > http://lxr.free-electrons.com/source/arch/arm64/include/asm/cache.h
> >
> > Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
> > ---
> >  config/defconfig_arm64-armv8a-linuxapp-gcc | 5 +++++
> >  config/defconfig_arm64-dpaa2-linuxapp-gcc  | 1 +
> >  config/defconfig_arm64-xgene1-linuxapp-gcc | 1 +
> >  3 files changed, 7 insertions(+)
> > --
> 
> Acked-by: Jianbo Liu <jianbo.liu@linaro.org>

Thomas,

Is it possible to merge this patch for v17.05-rc3?
Thomas Monjalon April 30, 2017, 9:10 p.m. UTC | #4 
28/04/2017 04:14, Jianbo Liu:
> On 27 April 2017 at 00:29, Jerin Jacob <jerin.jacob@caviumnetworks.com> wrote:
> > armv8 implementations may have 64B or 128B cache line.
> > Setting to the maximum available cache line size in generic config to
> > address minimum DMA alignment across all arm64 implementations.
> >
> > Increasing the cacheline size has no negative impact to cache invalidation
> > on systems with a smaller cache line.
> >
> > The need for the minimum DMA alignment has impact on functional aspects
> > of the platform so default config should cater the functional aspects.
> >
> > There is an impact on memory usage with this scheme, but that's not too
> > important for the single image arm64 distribution use case.
> >
> > The arm64 linux kernel followed the similar approach for single
> > arm64 image use case.
> > http://lxr.free-electrons.com/source/arch/arm64/include/asm/cache.h
> >
> > Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
> 
> Acked-by: Jianbo Liu <jianbo.liu@linaro.org>

Applied, thanks
diff mbox

Patch

diff --git a/config/defconfig_arm64-armv8a-linuxapp-gcc b/config/defconfig_arm64-armv8a-linuxapp-gcc
index 65888cef1..0faa2d3a3 100644
--- a/config/defconfig_arm64-armv8a-linuxapp-gcc
+++ b/config/defconfig_arm64-armv8a-linuxapp-gcc
@@ -42,6 +42,11 @@  CONFIG_RTE_FORCE_INTRINSICS=y
 CONFIG_RTE_TOOLCHAIN="gcc"
 CONFIG_RTE_TOOLCHAIN_GCC=y
 
+#Maximum available cache line size in arm64 implementations. Setting to maximum
+#available cache line size in generic config to address minimum DMA alignment
+#across all arm64 implementations.
+CONFIG_RTE_CACHE_LINE_SIZE=128
+
 CONFIG_RTE_EAL_IGB_UIO=n
 
 CONFIG_RTE_LIBRTE_FM10K_PMD=n
diff --git a/config/defconfig_arm64-dpaa2-linuxapp-gcc b/config/defconfig_arm64-dpaa2-linuxapp-gcc
index 010cb8092..314a0eceb 100644
--- a/config/defconfig_arm64-dpaa2-linuxapp-gcc
+++ b/config/defconfig_arm64-dpaa2-linuxapp-gcc
@@ -41,6 +41,7 @@  CONFIG_RTE_ARCH_ARM_TUNE="cortex-a57+fp+simd"
 #
 CONFIG_RTE_MAX_LCORE=8
 CONFIG_RTE_MAX_NUMA_NODES=1
+CONFIG_RTE_CACHE_LINE_SIZE=64
 
 CONFIG_RTE_PKTMBUF_HEADROOM=256
 
diff --git a/config/defconfig_arm64-xgene1-linuxapp-gcc b/config/defconfig_arm64-xgene1-linuxapp-gcc
index f096166b7..d8e544728 100644
--- a/config/defconfig_arm64-xgene1-linuxapp-gcc
+++ b/config/defconfig_arm64-xgene1-linuxapp-gcc
@@ -32,3 +32,4 @@ 
 #include "defconfig_arm64-armv8a-linuxapp-gcc"
 
 CONFIG_RTE_MACHINE="xgene1"
+CONFIG_RTE_CACHE_LINE_SIZE=64