@@ -78,13 +78,13 @@ struct cperf_test_vector {
struct {
uint8_t *data;
- phys_addr_t phys_addr;
+ iova_addr_t phys_addr;
uint16_t length;
} aad;
struct {
uint8_t *data;
- phys_addr_t phys_addr;
+ iova_addr_t phys_addr;
uint16_t length;
} digest;
@@ -712,7 +712,7 @@ The following are some guidelines for use of Doxygen in the DPDK API documentati
/**< Virtual address of the first mempool object. */
uintptr_t elt_va_end;
/**< Virtual address of the <size + 1> mempool object. */
- phys_addr_t elt_pa[MEMPOOL_PG_NUM_DEFAULT];
+ iova_addr_t elt_pa[MEMPOOL_PG_NUM_DEFAULT];
/**< Array of physical page addresses for the mempool buffer. */
This doesn't have an effect on the rendered documentation but it is confusing for the developer reading the code.
@@ -731,7 +731,7 @@ The following are some guidelines for use of Doxygen in the DPDK API documentati
/** Virtual address of the <size + 1> mempool object. */
uintptr_t elt_va_end;
/** Array of physical page addresses for the mempool buffer. */
- phys_addr_t elt_pa[MEMPOOL_PG_NUM_DEFAULT];
+ iova_addr_t elt_pa[MEMPOOL_PG_NUM_DEFAULT];
* Check for Doxygen warnings in new code by checking the API documentation build::
@@ -539,12 +539,12 @@ chain.
struct {
uint8_t *data;
- phys_addr_t phys_addr;
+ iova_addr_t phys_addr;
} digest; /**< Digest parameters */
struct {
uint8_t *data;
- phys_addr_t phys_addr;
+ iova_addr_t phys_addr;
} aad;
/**< Additional authentication parameters */
} aead;
@@ -566,7 +566,7 @@ chain.
struct {
uint8_t *data;
- phys_addr_t phys_addr;
+ iova_addr_t phys_addr;
} digest; /**< Digest parameters */
} auth;
};
@@ -271,9 +271,9 @@ enum qbman_fd_format {
#define DPAA2_EQ_RESP_ALWAYS 1
#ifdef RTE_LIBRTE_DPAA2_USE_PHYS_IOVA
-static void *dpaa2_mem_ptov(phys_addr_t paddr) __attribute__((unused));
+static void *dpaa2_mem_ptov(iova_addr_t paddr) __attribute__((unused));
/* todo - this is costly, need to write a fast coversion routine */
-static void *dpaa2_mem_ptov(phys_addr_t paddr)
+static void *dpaa2_mem_ptov(iova_addr_t paddr)
{
const struct rte_memseg *memseg = rte_eal_get_physmem_layout();
int i;
@@ -287,8 +287,8 @@ static void *dpaa2_mem_ptov(phys_addr_t paddr)
return NULL;
}
-static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr) __attribute__((unused));
-static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr)
+static iova_addr_t dpaa2_mem_vtop(uint64_t vaddr) __attribute__((unused));
+static iova_addr_t dpaa2_mem_vtop(uint64_t vaddr)
{
const struct rte_memseg *memseg = rte_eal_get_physmem_layout();
int i;
@@ -299,7 +299,7 @@ static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr)
return memseg[i].phys_addr
+ (vaddr - memseg[i].addr_64);
}
- return (phys_addr_t)(NULL);
+ return (iova_addr_t)(NULL);
}
/**
@@ -320,13 +320,13 @@ static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr)
/**
* macro to convert IOVA to Virtual address
*/
-#define DPAA2_IOVA_TO_VADDR(_iova) dpaa2_mem_ptov((phys_addr_t)(_iova))
+#define DPAA2_IOVA_TO_VADDR(_iova) dpaa2_mem_ptov((iova_addr_t)(_iova))
/**
* macro to convert modify the memory containing IOVA to Virtual address
*/
#define DPAA2_MODIFY_IOVA_TO_VADDR(_mem, _type) \
- {_mem = (_type)(dpaa2_mem_ptov((phys_addr_t)(_mem))); }
+ {_mem = (_type)(dpaa2_mem_ptov((iova_addr_t)(_mem))); }
#else /* RTE_LIBRTE_DPAA2_USE_PHYS_IOVA */
@@ -104,8 +104,8 @@ struct qat_alg_buf_list {
struct qat_crypto_op_cookie {
struct qat_alg_buf_list qat_sgl_list_src;
struct qat_alg_buf_list qat_sgl_list_dst;
- phys_addr_t qat_sgl_src_phys_addr;
- phys_addr_t qat_sgl_dst_phys_addr;
+ iova_addr_t qat_sgl_src_phys_addr;
+ iova_addr_t qat_sgl_dst_phys_addr;
};
/* Common content descriptor */
@@ -124,7 +124,7 @@ struct qat_session {
void *bpi_ctx;
struct qat_alg_cd cd;
uint8_t *cd_cur_ptr;
- phys_addr_t cd_paddr;
+ iova_addr_t cd_paddr;
struct icp_qat_fw_la_bulk_req fw_req;
uint8_t aad_len;
struct qat_crypto_instance *inst;
@@ -63,7 +63,7 @@ enum qat_device_gen {
struct qat_queue {
char memz_name[RTE_MEMZONE_NAMESIZE];
void *base_addr; /* Base address */
- phys_addr_t base_phys_addr; /* Queue physical address */
+ iova_addr_t base_phys_addr; /* Queue physical address */
uint32_t head; /* Shadow copy of the head */
uint32_t tail; /* Shadow copy of the tail */
uint32_t modulo;
@@ -39,7 +39,7 @@
struct buf_pool_cfg {
void *addr;
/**< The address from where DPAA2 will carve out the buffers */
- phys_addr_t phys_addr;
+ iova_addr_t phys_addr;
/**< Physical address of the memory provided in addr */
uint32_t num;
/**< Number of buffers */
@@ -93,7 +93,7 @@ ark_ddm_reset(struct ark_ddm_t *ddm)
}
void
-ark_ddm_setup(struct ark_ddm_t *ddm, phys_addr_t cons_addr, uint32_t interval)
+ark_ddm_setup(struct ark_ddm_t *ddm, iova_addr_t cons_addr, uint32_t interval)
{
ddm->setup.cons_write_index_addr = cons_addr;
ddm->setup.write_index_interval = interval / 4; /* 4 ns period */
@@ -127,7 +127,7 @@ struct ark_ddm_cpld_ps_t {
#define ARK_DDM_SETUP 0x00e0
struct ark_ddm_setup_t {
- phys_addr_t cons_write_index_addr;
+ iova_addr_t cons_write_index_addr;
uint32_t write_index_interval; /* 4ns each */
volatile uint32_t cons_index;
};
@@ -165,7 +165,7 @@ void ark_ddm_start(struct ark_ddm_t *ddm);
int ark_ddm_stop(struct ark_ddm_t *ddm, const int wait);
void ark_ddm_reset(struct ark_ddm_t *ddm);
void ark_ddm_stats_reset(struct ark_ddm_t *ddm);
-void ark_ddm_setup(struct ark_ddm_t *ddm, phys_addr_t cons_addr,
+void ark_ddm_setup(struct ark_ddm_t *ddm, iova_addr_t cons_addr,
uint32_t interval);
void ark_ddm_dump_stats(struct ark_ddm_t *ddm, const char *msg);
void ark_ddm_dump(struct ark_ddm_t *ddm, const char *msg);
@@ -62,7 +62,7 @@ struct ark_rx_queue {
struct rte_mbuf **reserve_q;
/* array of physical addresses of the mbuf data pointer */
/* This point is a virtual address */
- phys_addr_t *paddress_q;
+ iova_addr_t *paddress_q;
struct rte_mempool *mb_pool;
struct ark_udm_t *udm;
@@ -96,9 +96,9 @@ eth_ark_rx_hw_setup(struct rte_eth_dev *dev,
struct ark_rx_queue *queue,
uint16_t rx_queue_id __rte_unused, uint16_t rx_queue_idx)
{
- phys_addr_t queue_base;
- phys_addr_t phys_addr_q_base;
- phys_addr_t phys_addr_prod_index;
+ iova_addr_t queue_base;
+ iova_addr_t phys_addr_q_base;
+ iova_addr_t phys_addr_prod_index;
queue_base = rte_malloc_virt2phy(queue);
phys_addr_prod_index = queue_base +
@@ -107,7 +107,7 @@ eth_ark_rx_hw_setup(struct rte_eth_dev *dev,
phys_addr_q_base = rte_malloc_virt2phy(queue->paddress_q);
/* Verify HW */
- if (ark_mpu_verify(queue->mpu, sizeof(phys_addr_t))) {
+ if (ark_mpu_verify(queue->mpu, sizeof(iova_addr_t))) {
PMD_DRV_LOG(ERR, "Illegal configuration rx queue\n");
return -1;
}
@@ -205,7 +205,7 @@ eth_ark_dev_rx_queue_setup(struct rte_eth_dev *dev,
socket_id);
queue->paddress_q =
rte_zmalloc_socket("Ark_rx_queue paddr",
- nb_desc * sizeof(phys_addr_t),
+ nb_desc * sizeof(iova_addr_t),
64,
socket_id);
@@ -311,7 +311,7 @@ eth_ark_tx_queue_setup(struct rte_eth_dev *dev,
static int
eth_ark_tx_hw_queue_config(struct ark_tx_queue *queue)
{
- phys_addr_t queue_base, ring_base, cons_index_addr;
+ iova_addr_t queue_base, ring_base, cons_index_addr;
uint32_t write_interval_ns;
/* Verify HW -- MPU */
@@ -118,7 +118,7 @@ ark_mpu_reset_stats(struct ark_mpu_t *mpu)
}
int
-ark_mpu_configure(struct ark_mpu_t *mpu, phys_addr_t ring, uint32_t ring_size,
+ark_mpu_configure(struct ark_mpu_t *mpu, iova_addr_t ring, uint32_t ring_size,
int is_tx)
{
ark_mpu_reset(mpu);
@@ -75,7 +75,7 @@ struct ark_mpu_hw_t {
#define ARK_MPU_CFG 0x040
struct ark_mpu_cfg_t {
- phys_addr_t ring_base; /* phys_addr_t is a uint64_t */
+ iova_addr_t ring_base; /* iova_addr_t is a uint64_t */
uint32_t ring_size;
uint32_t ring_mask;
uint32_t min_host_move;
@@ -137,7 +137,7 @@ int ark_mpu_verify(struct ark_mpu_t *mpu, uint32_t obj_size);
void ark_mpu_stop(struct ark_mpu_t *mpu);
void ark_mpu_start(struct ark_mpu_t *mpu);
int ark_mpu_reset(struct ark_mpu_t *mpu);
-int ark_mpu_configure(struct ark_mpu_t *mpu, phys_addr_t ring,
+int ark_mpu_configure(struct ark_mpu_t *mpu, iova_addr_t ring,
uint32_t ring_size, int is_tx);
void ark_mpu_dump(struct ark_mpu_t *mpu, const char *msg, uint16_t idx);
@@ -122,7 +122,7 @@ ark_udm_configure(struct ark_udm_t *udm,
}
void
-ark_udm_write_addr(struct ark_udm_t *udm, phys_addr_t addr)
+ark_udm_write_addr(struct ark_udm_t *udm, iova_addr_t addr)
{
udm->rt_cfg.hw_prod_addr = addr;
}
@@ -137,7 +137,7 @@ struct ark_udm_tlp_ps_t {
#define ARK_UDM_RT_CFG 0x00e0
struct ark_udm_rt_cfg_t {
- phys_addr_t hw_prod_addr;
+ iova_addr_t hw_prod_addr;
uint32_t write_interval; /* 4ns cycles */
volatile uint32_t prod_idx; /* RO */
};
@@ -171,7 +171,7 @@ void ark_udm_configure(struct ark_udm_t *udm,
uint32_t headroom,
uint32_t dataroom,
uint32_t write_interval_ns);
-void ark_udm_write_addr(struct ark_udm_t *udm, phys_addr_t addr);
+void ark_udm_write_addr(struct ark_udm_t *udm, iova_addr_t addr);
void ark_udm_stats_reset(struct ark_udm_t *udm);
void ark_udm_dump_stats(struct ark_udm_t *udm, const char *msg);
void ark_udm_dump_queue_stats(struct ark_udm_t *udm, const char *msg,
@@ -387,7 +387,7 @@ avp_dev_translate_buffer(struct avp_dev *avp, void *host_mbuf_address)
/* translate from host physical address to guest virtual address */
static void *
avp_dev_translate_address(struct rte_eth_dev *eth_dev,
- phys_addr_t host_phys_addr)
+ iova_addr_t host_phys_addr)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
struct rte_mem_resource *resource;
@@ -243,7 +243,7 @@ struct rte_avp_desc {
*/
struct rte_avp_memmap {
void *addr;
- phys_addr_t phys_addr;
+ iova_addr_t phys_addr;
uint64_t length;
};
@@ -345,7 +345,7 @@ RTE_AVP_MAKE_VERSION(RTE_AVP_RELEASE_VERSION_1, \
*/
struct rte_avp_mempool_info {
void *addr;
- phys_addr_t phys_addr;
+ iova_addr_t phys_addr;
uint64_t length;
};
@@ -359,10 +359,10 @@ struct rte_avp_device_info {
char ifname[RTE_AVP_NAMESIZE]; /**< Network device name for AVP */
- phys_addr_t tx_phys;
- phys_addr_t rx_phys;
- phys_addr_t alloc_phys;
- phys_addr_t free_phys;
+ iova_addr_t tx_phys;
+ iova_addr_t rx_phys;
+ iova_addr_t alloc_phys;
+ iova_addr_t free_phys;
uint32_t features; /**< Supported feature bitmap */
uint8_t min_rx_queues; /**< Minimum supported receive/free queues */
@@ -379,14 +379,14 @@ struct rte_avp_device_info {
uint32_t free_size; /**< Size of each free queue */
/* Used by Ethtool */
- phys_addr_t req_phys;
- phys_addr_t resp_phys;
- phys_addr_t sync_phys;
+ iova_addr_t req_phys;
+ iova_addr_t resp_phys;
+ iova_addr_t sync_phys;
void *sync_va;
/* mbuf mempool (used when a single memory area is supported) */
void *mbuf_va;
- phys_addr_t mbuf_phys;
+ iova_addr_t mbuf_phys;
/* mbuf mempools */
struct rte_avp_mempool_info pool[RTE_AVP_MAX_MEMPOOLS];
@@ -419,7 +419,7 @@ void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32)
}
void
-bnx2x_write_dmae(struct bnx2x_softc *sc, phys_addr_t dma_addr, uint32_t dst_addr,
+bnx2x_write_dmae(struct bnx2x_softc *sc, iova_addr_t dma_addr, uint32_t dst_addr,
uint32_t len32)
{
struct dmae_command dmae;
@@ -447,7 +447,7 @@ bnx2x_write_dmae(struct bnx2x_softc *sc, phys_addr_t dma_addr, uint32_t dst_addr
}
static void
-bnx2x_write_dmae_phys_len(struct bnx2x_softc *sc, phys_addr_t phys_addr,
+bnx2x_write_dmae_phys_len(struct bnx2x_softc *sc, iova_addr_t phys_addr,
uint32_t addr, uint32_t len)
{
uint32_t dmae_wr_max = DMAE_LEN32_WR_MAX(sc);
@@ -823,14 +823,14 @@ bnx2x_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
static void
__storm_memset_dma_mapping(struct bnx2x_softc *sc, uint32_t addr,
- phys_addr_t mapping)
+ iova_addr_t mapping)
{
REG_WR(sc, addr, U64_LO(mapping));
REG_WR(sc, (addr + 4), U64_HI(mapping));
}
static void
-storm_memset_spq_addr(struct bnx2x_softc *sc, phys_addr_t mapping,
+storm_memset_spq_addr(struct bnx2x_softc *sc, iova_addr_t mapping,
uint16_t abs_fid)
{
uint32_t addr = (XSEM_REG_FAST_MEMORY +
@@ -1498,7 +1498,7 @@ bnx2x_set_q_rx_mode(struct bnx2x_softc *sc, uint8_t cl_id,
ramrod_param.rdata = BNX2X_SP(sc, rx_mode_rdata);
ramrod_param.rdata_mapping =
- (phys_addr_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata),
+ (iova_addr_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata),
bnx2x_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
ramrod_param.ramrod_flags = ramrod_flags;
@@ -4599,9 +4599,9 @@ static void bnx2x_init_func_obj(struct bnx2x_softc *sc)
ecore_init_func_obj(sc,
&sc->func_obj,
BNX2X_SP(sc, func_rdata),
- (phys_addr_t)BNX2X_SP_MAPPING(sc, func_rdata),
+ (iova_addr_t)BNX2X_SP_MAPPING(sc, func_rdata),
BNX2X_SP(sc, func_afex_rdata),
- (phys_addr_t)BNX2X_SP_MAPPING(sc, func_afex_rdata),
+ (iova_addr_t)BNX2X_SP_MAPPING(sc, func_afex_rdata),
&bnx2x_func_sp_drv);
}
@@ -4772,7 +4772,7 @@ static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
}
static void
-bnx2x_init_sb(struct bnx2x_softc *sc, phys_addr_t busaddr, int vfid,
+bnx2x_init_sb(struct bnx2x_softc *sc, iova_addr_t busaddr, int vfid,
uint8_t vf_valid, int fw_sb_id, int igu_sb_id)
{
struct hc_status_block_data_e2 sb_data_e2;
@@ -4918,7 +4918,7 @@ static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx)
sc->max_cos,
SC_FUNC(sc),
BNX2X_SP(sc, q_rdata),
- (phys_addr_t)BNX2X_SP_MAPPING(sc, q_rdata),
+ (iova_addr_t)BNX2X_SP_MAPPING(sc, q_rdata),
q_type);
/* configure classification DBs */
@@ -4928,7 +4928,7 @@ static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx)
idx,
SC_FUNC(sc),
BNX2X_SP(sc, mac_rdata),
- (phys_addr_t)BNX2X_SP_MAPPING(sc, mac_rdata),
+ (iova_addr_t)BNX2X_SP_MAPPING(sc, mac_rdata),
ECORE_FILTER_MAC_PENDING, &sc->sp_state,
ECORE_OBJ_TYPE_RX_TX, &sc->macs_pool);
}
@@ -5028,7 +5028,7 @@ static void bnx2x_init_tx_rings(struct bnx2x_softc *sc)
static void bnx2x_init_def_sb(struct bnx2x_softc *sc)
{
struct host_sp_status_block *def_sb = sc->def_sb;
- phys_addr_t mapping = sc->def_sb_dma.paddr;
+ iova_addr_t mapping = sc->def_sb_dma.paddr;
int igu_sp_sb_index;
int igu_seg_id;
int port = SC_PORT(sc);
@@ -5700,7 +5700,7 @@ static void bnx2x_init_objs(struct bnx2x_softc *sc)
SC_FUNC(sc),
SC_FUNC(sc),
BNX2X_SP(sc, mcast_rdata),
- (phys_addr_t)BNX2X_SP_MAPPING(sc, mcast_rdata),
+ (iova_addr_t)BNX2X_SP_MAPPING(sc, mcast_rdata),
ECORE_FILTER_MCAST_PENDING,
&sc->sp_state, o_type);
@@ -5724,7 +5724,7 @@ static void bnx2x_init_objs(struct bnx2x_softc *sc)
SC_FUNC(sc),
SC_FUNC(sc),
BNX2X_SP(sc, rss_rdata),
- (phys_addr_t)BNX2X_SP_MAPPING(sc, rss_rdata),
+ (iova_addr_t)BNX2X_SP_MAPPING(sc, rss_rdata),
ECORE_FILTER_RSS_CONF_PENDING,
&sc->sp_state, ECORE_OBJ_TYPE_RX);
}
@@ -6445,9 +6445,9 @@ bnx2x_pf_rx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
pause->pri_map = 1;
/* rxq setup */
- rxq_init->dscr_map = (phys_addr_t)rxq->rx_ring_phys_addr;
- rxq_init->rcq_map = (phys_addr_t)rxq->cq_ring_phys_addr;
- rxq_init->rcq_np_map = (phys_addr_t)(rxq->cq_ring_phys_addr +
+ rxq_init->dscr_map = (iova_addr_t)rxq->rx_ring_phys_addr;
+ rxq_init->rcq_map = (iova_addr_t)rxq->cq_ring_phys_addr;
+ rxq_init->rcq_np_map = (iova_addr_t)(rxq->cq_ring_phys_addr +
BNX2X_PAGE_SIZE);
/*
@@ -6486,7 +6486,7 @@ bnx2x_pf_tx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
return;
}
- txq_init->dscr_map = (phys_addr_t)txq->tx_ring_phys_addr;
+ txq_init->dscr_map = (iova_addr_t)txq->tx_ring_phys_addr;
txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
txq_init->fw_sb_id = fp->fw_sb_id;
@@ -11059,7 +11059,7 @@ static int bnx2x_init_hw_func(struct bnx2x_softc *sc)
for (i = 0; i < L2_ILT_LINES(sc); i++) {
ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt;
ilt->lines[cdu_ilt_start + i].page_mapping =
- (phys_addr_t)sc->context[i].vcxt_dma.paddr;
+ (iova_addr_t)sc->context[i].vcxt_dma.paddr;
ilt->lines[cdu_ilt_start + i].size = sc->context[i].size;
}
ecore_ilt_init_op(sc, INITOP_SET);
@@ -11357,7 +11357,7 @@ static void bnx2x_reset_port(struct bnx2x_softc *sc)
}
}
-static void bnx2x_ilt_wr(struct bnx2x_softc *sc, uint32_t index, phys_addr_t addr)
+static void bnx2x_ilt_wr(struct bnx2x_softc *sc, uint32_t index, iova_addr_t addr)
{
int reg;
uint32_t wb_write[2];
@@ -11587,7 +11587,7 @@ static int ecore_gunzip(struct bnx2x_softc *sc, const uint8_t * zbuf, int len)
}
static void
-ecore_write_dmae_phys_len(struct bnx2x_softc *sc, phys_addr_t phys_addr,
+ecore_write_dmae_phys_len(struct bnx2x_softc *sc, iova_addr_t phys_addr,
uint32_t addr, uint32_t len)
{
bnx2x_write_dmae_phys_len(sc, phys_addr, addr, len);
@@ -317,7 +317,7 @@ struct bnx2x_bar {
/* Used to manage DMA allocations. */
struct bnx2x_dma {
struct bnx2x_softc *sc;
- phys_addr_t paddr;
+ iova_addr_t paddr;
void *vaddr;
int nseg;
char msg[RTE_MEMZONE_NAMESIZE - 6];
@@ -370,10 +370,10 @@ struct bnx2x_fastpath {
struct bnx2x_dma sb_dma;
union bnx2x_host_hc_status_block status_block;
- phys_addr_t tx_desc_mapping;
+ iova_addr_t tx_desc_mapping;
- phys_addr_t rx_desc_mapping;
- phys_addr_t rx_comp_mapping;
+ iova_addr_t rx_desc_mapping;
+ iova_addr_t rx_comp_mapping;
uint16_t *sb_index_values;
uint16_t *sb_running_index;
@@ -468,7 +468,7 @@ union cdu_context {
struct hw_context {
struct bnx2x_dma vcxt_dma;
union cdu_context *vcxt;
- //phys_addr_t cxt_mapping;
+ //iova_addr_t cxt_mapping;
size_t size;
};
@@ -1242,7 +1242,7 @@ struct bnx2x_softc {
uint32_t gz_outlen;
#define GUNZIP_BUF(sc) (sc->gz_buf)
#define GUNZIP_OUTLEN(sc) (sc->gz_outlen)
-#define GUNZIP_PHYS(sc) (phys_addr_t)(sc->gz_buf_dma.paddr)
+#define GUNZIP_PHYS(sc) (iova_addr_t)(sc->gz_buf_dma.paddr)
#define FW_BUF_SIZE 0x40000
struct raw_op *init_ops;
@@ -1310,14 +1310,14 @@ struct bnx2x_softc {
*/
int fw_stats_req_size;
struct bnx2x_fw_stats_req *fw_stats_req;
- phys_addr_t fw_stats_req_mapping;
+ iova_addr_t fw_stats_req_mapping;
/*
* FW statistics data shortcut (points at the beginning of fw_stats
* buffer + fw_stats_req_size).
*/
int fw_stats_data_size;
struct bnx2x_fw_stats_data *fw_stats_data;
- phys_addr_t fw_stats_data_mapping;
+ iova_addr_t fw_stats_data_mapping;
/* tracking a pending STAT_QUERY ramrod */
uint16_t stats_pending;
@@ -1402,8 +1402,8 @@ union bnx2x_stats_show_data {
#define FUNC_FLG_LEADING 0x0020 /* PF only */
struct bnx2x_func_init_params {
- phys_addr_t fw_stat_map; /* (dma) valid if FUNC_FLG_STATS */
- phys_addr_t spq_map; /* (dma) valid if FUNC_FLG_SPQ */
+ iova_addr_t fw_stat_map; /* (dma) valid if FUNC_FLG_STATS */
+ iova_addr_t spq_map; /* (dma) valid if FUNC_FLG_SPQ */
uint16_t func_flgs;
uint16_t func_id; /* abs function id */
uint16_t pf_id;
@@ -1748,7 +1748,7 @@ uint32_t bnx2x_dmae_opcode(struct bnx2x_softc *sc, uint8_t src_type,
uint8_t comp_type);
void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx);
void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32);
-void bnx2x_write_dmae(struct bnx2x_softc *sc, phys_addr_t dma_addr,
+void bnx2x_write_dmae(struct bnx2x_softc *sc, iova_addr_t dma_addr,
uint32_t dst_addr, uint32_t len32);
void bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
uint32_t cid);
@@ -71,8 +71,8 @@ bnx2x_dev_rx_queue_setup(struct rte_eth_dev *dev,
struct bnx2x_softc *sc = dev->data->dev_private;
struct bnx2x_fastpath *fp = &sc->fp[queue_idx];
struct eth_rx_cqe_next_page *nextpg;
- phys_addr_t *rx_bd;
- phys_addr_t busaddr;
+ iova_addr_t *rx_bd;
+ iova_addr_t busaddr;
/* First allocate the rx queue data structure */
rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct bnx2x_rx_queue),
@@ -1338,7 +1338,7 @@ bnx2x_prep_fw_stats_req(struct bnx2x_softc *sc)
int i;
int first_queue_query_index;
struct stats_query_header *stats_hdr = &sc->fw_stats_req->hdr;
- phys_addr_t cur_data_offset;
+ iova_addr_t cur_data_offset;
struct stats_query_entry *cur_query_entry;
stats_hdr->cmd_num = sc->fw_stats_num;
@@ -113,7 +113,7 @@ bnx2x_vf_finalize(struct bnx2x_softc *sc,
#define BNX2X_VF_CHANNEL_TRIES 100
static int
-bnx2x_do_req4pf(struct bnx2x_softc *sc, phys_addr_t phys_addr)
+bnx2x_do_req4pf(struct bnx2x_softc *sc, iova_addr_t phys_addr)
{
uint8_t *status = &sc->vf2pf_mbox->resp.common_reply.status;
uint8_t i;
@@ -36,7 +36,7 @@
#include "ecore_reg.h"
struct bnx2x_softc;
-typedef phys_addr_t ecore_dma_addr_t; /* expected to be 64 bit wide */
+typedef iova_addr_t ecore_dma_addr_t; /* expected to be 64 bit wide */
typedef volatile int ecore_atomic_t;
@@ -132,7 +132,7 @@ struct bnxt_pf_info {
uint16_t max_vfs;
uint32_t func_cfg_flags;
void *vf_req_buf;
- phys_addr_t vf_req_buf_dma_addr;
+ iova_addr_t vf_req_buf_dma_addr;
uint32_t vf_req_fwd[8];
uint16_t total_vnics;
struct bnxt_child_vf_info *vf_info;
@@ -194,14 +194,14 @@ struct bnxt {
struct bnxt_rx_queue **rx_queues;
const void *rx_mem_zone;
struct rx_port_stats *hw_rx_port_stats;
- phys_addr_t hw_rx_port_stats_map;
+ iova_addr_t hw_rx_port_stats_map;
unsigned int tx_nr_rings;
unsigned int tx_cp_nr_rings;
struct bnxt_tx_queue **tx_queues;
const void *tx_mem_zone;
struct tx_port_stats *hw_tx_port_stats;
- phys_addr_t hw_tx_port_stats_map;
+ iova_addr_t hw_tx_port_stats_map;
/* Default completion ring */
struct bnxt_cp_ring_info *def_cp_ring;
@@ -227,9 +227,9 @@ struct bnxt {
uint16_t hwrm_cmd_seq;
void *hwrm_cmd_resp_addr;
- phys_addr_t hwrm_cmd_resp_dma_addr;
+ iova_addr_t hwrm_cmd_resp_dma_addr;
void *hwrm_short_cmd_req_addr;
- phys_addr_t hwrm_short_cmd_req_dma_addr;
+ iova_addr_t hwrm_short_cmd_req_dma_addr;
rte_spinlock_t hwrm_lock;
uint16_t max_req_len;
uint16_t max_resp_len;
@@ -82,10 +82,10 @@ struct bnxt_cp_ring_info {
struct cmpl_base *cp_desc_ring;
- phys_addr_t cp_desc_mapping;
+ iova_addr_t cp_desc_mapping;
struct ctx_hw_stats *hw_stats;
- phys_addr_t hw_stats_map;
+ iova_addr_t hw_stats_map;
uint32_t hw_stats_ctx_id;
struct bnxt_ring *cp_ring_struct;
@@ -1628,7 +1628,7 @@ bnxt_dev_init(struct rte_eth_dev *eth_dev)
const struct rte_memzone *mz = NULL;
static int version_printed;
uint32_t total_alloc_len;
- phys_addr_t mz_phys_addr;
+ iova_addr_t mz_phys_addr;
struct bnxt *bp;
int rc;
@@ -98,7 +98,7 @@ int bnxt_alloc_rings(struct bnxt *bp, uint16_t qidx,
struct rte_pci_device *pdev = bp->pdev;
const struct rte_memzone *mz = NULL;
char mz_name[RTE_MEMZONE_NAMESIZE];
- phys_addr_t mz_phys_addr;
+ iova_addr_t mz_phys_addr;
int sz;
int stats_len = (tx_ring_info || rx_ring_info) ?
@@ -70,7 +70,7 @@
struct bnxt_ring {
void *bd;
- phys_addr_t bd_dma;
+ iova_addr_t bd_dma;
uint32_t ring_size;
uint32_t ring_mask;
@@ -85,8 +85,8 @@ struct bnxt_rx_ring_info {
struct bnxt_sw_rx_bd *rx_buf_ring; /* sw ring */
struct bnxt_sw_rx_bd *ag_buf_ring; /* sw ring */
- phys_addr_t rx_desc_mapping;
- phys_addr_t ag_desc_mapping;
+ iova_addr_t rx_desc_mapping;
+ iova_addr_t ag_desc_mapping;
struct bnxt_ring *rx_ring_struct;
struct bnxt_ring *ag_ring_struct;
@@ -49,7 +49,7 @@ struct bnxt_tx_ring_info {
struct tx_bd_long *tx_desc_ring;
struct bnxt_sw_tx_bd *tx_buf_ring;
- phys_addr_t tx_desc_mapping;
+ iova_addr_t tx_desc_mapping;
#define BNXT_DEV_STATE_CLOSING 0x1
uint32_t dev_state;
@@ -174,7 +174,7 @@ int bnxt_alloc_vnic_attributes(struct bnxt *bp)
BNXT_MAX_MC_ADDRS * ETHER_ADDR_LEN);
uint16_t max_vnics;
int i;
- phys_addr_t mz_phys_addr;
+ iova_addr_t mz_phys_addr;
max_vnics = bp->max_vnics;
snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
@@ -53,11 +53,11 @@ struct bnxt_vnic_info {
uint16_t dflt_ring_grp;
uint16_t mru;
uint16_t hash_type;
- phys_addr_t rss_table_dma_addr;
+ iova_addr_t rss_table_dma_addr;
uint16_t *rss_table;
- phys_addr_t rss_hash_key_dma_addr;
+ iova_addr_t rss_hash_key_dma_addr;
void *rss_hash_key;
- phys_addr_t mc_list_dma_addr;
+ iova_addr_t mc_list_dma_addr;
char *mc_list;
uint32_t mc_addr_cnt;
#define BNXT_MAX_MC_ADDRS 16
@@ -1744,7 +1744,7 @@ lio_dev_xmit_pkts(void *tx_queue, struct rte_mbuf **pkts, uint16_t nb_pkts)
} else {
struct lio_buf_free_info *finfo;
struct lio_gather *g;
- phys_addr_t phyaddr;
+ iova_addr_t phyaddr;
int i, frags;
finfo = (struct lio_buf_free_info *)rte_malloc(NULL,
@@ -686,7 +686,7 @@ lio_swap_8B_data(uint64_t *data, uint32_t blocks)
static inline uint64_t
lio_map_ring(void *buf)
{
- phys_addr_t dma_addr;
+ iova_addr_t dma_addr;
dma_addr = rte_mbuf_data_dma_addr_default(((struct rte_mbuf *)buf));
@@ -696,7 +696,7 @@ lio_map_ring(void *buf)
static inline uint64_t
lio_map_ring_info(struct lio_droq *droq, uint32_t i)
{
- phys_addr_t dma_addr;
+ iova_addr_t dma_addr;
dma_addr = droq->info_list_dma + (i * LIO_DROQ_INFO_SIZE);
@@ -60,7 +60,7 @@ typedef u32 OSAL_BE32;
#define osal_uintptr_t uintptr_t
-typedef phys_addr_t dma_addr_t;
+typedef iova_addr_t dma_addr_t;
typedef rte_spinlock_t osal_spinlock_t;
@@ -253,7 +253,7 @@ typedef struct __efsys_identifier_s efsys_identifier_t;
/* DMA */
-typedef phys_addr_t efsys_dma_addr_t;
+typedef iova_addr_t efsys_dma_addr_t;
typedef struct efsys_mem_s {
const struct rte_memzone *esm_mz;
@@ -177,7 +177,7 @@ sfc_ef10_rx_qrefill(struct sfc_ef10_rxq *rxq)
++i, ++id) {
struct rte_mbuf *m = objs[i];
struct sfc_ef10_rx_sw_desc *rxd;
- phys_addr_t phys_addr;
+ iova_addr_t phys_addr;
SFC_ASSERT((id & ~ptr_mask) == 0);
rxd = &rxq->sw_ring[id];
@@ -177,7 +177,7 @@ sfc_ef10_tx_reap(struct sfc_ef10_txq *txq)
}
static void
-sfc_ef10_tx_qdesc_dma_create(phys_addr_t addr, uint16_t size, bool eop,
+sfc_ef10_tx_qdesc_dma_create(iova_addr_t addr, uint16_t size, bool eop,
efx_qword_t *edp)
{
EFX_POPULATE_QWORD_4(*edp,
@@ -323,7 +323,7 @@ sfc_ef10_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
pkt_len = m_seg->pkt_len;
do {
- phys_addr_t seg_addr = rte_mbuf_data_dma_addr(m_seg);
+ iova_addr_t seg_addr = rte_mbuf_data_dma_addr(m_seg);
unsigned int seg_len = rte_pktmbuf_data_len(m_seg);
SFC_ASSERT(seg_len <= SFC_EF10_TX_DMA_DESC_LEN_MAX);
@@ -509,7 +509,7 @@ nicvf_qset_rbdr_precharge(void *dev, struct nicvf *nic,
struct rbdr_entry_t *desc, *desc0;
struct nicvf_rbdr *rbdr = nic->rbdr;
uint32_t count;
- nicvf_phys_addr_t phy;
+ nicvf_iova_addr_t phy;
assert(rbdr != NULL);
desc = rbdr->desc;
@@ -88,7 +88,7 @@ enum nicvf_err_e {
NICVF_ERR_RSS_GET_SZ, /* -8171 */
};
-typedef nicvf_phys_addr_t (*rbdr_pool_get_handler)(void *dev, void *opaque);
+typedef nicvf_iova_addr_t (*rbdr_pool_get_handler)(void *dev, void *opaque);
struct nicvf_hw_rx_qstats {
uint64_t q_rx_bytes;
@@ -213,7 +213,7 @@
#define NICVF_STATIC_ASSERT(s) _Static_assert(s, #s)
#define assert_primary(nic) assert((nic)->sqs_mode == 0)
-typedef uint64_t nicvf_phys_addr_t;
+typedef uint64_t nicvf_iova_addr_t;
/* vNIC HW Enumerations */
@@ -840,7 +840,7 @@ struct rbdr_entry_t {
uint64_t buf_addr:42;
uint64_t cache_align:7;
};
- nicvf_phys_addr_t full_addr;
+ nicvf_iova_addr_t full_addr;
};
#else
union {
@@ -849,7 +849,7 @@ struct rbdr_entry_t {
uint64_t buf_addr:42;
uint64_t rsvd0:15;
};
- nicvf_phys_addr_t full_addr;
+ nicvf_iova_addr_t full_addr;
};
#endif
};
@@ -677,7 +677,7 @@ nicvf_qset_rbdr_alloc(struct rte_eth_dev *dev, struct nicvf *nic,
static void
nicvf_rbdr_release_mbuf(struct rte_eth_dev *dev, struct nicvf *nic,
- nicvf_phys_addr_t phy)
+ nicvf_iova_addr_t phy)
{
uint16_t qidx;
void *obj;
@@ -1419,7 +1419,7 @@ nicvf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
};
}
-static nicvf_phys_addr_t
+static nicvf_iova_addr_t
rbdr_rte_mempool_get(void *dev, void *opaque)
{
uint16_t qidx;
@@ -104,7 +104,7 @@ nicvf_netdev_qidx(struct nicvf *nic, uint8_t local_qidx)
* P = V - offset
*/
static inline uintptr_t
-nicvf_mbuff_phy2virt(phys_addr_t phy, uint64_t mbuf_phys_off)
+nicvf_mbuff_phy2virt(iova_addr_t phy, uint64_t mbuf_phys_off)
{
return (uintptr_t)(phy + mbuf_phys_off);
}
@@ -112,7 +112,7 @@ nicvf_mbuff_phy2virt(phys_addr_t phy, uint64_t mbuf_phys_off)
static inline uintptr_t
nicvf_mbuff_virt2phy(uintptr_t virt, uint64_t mbuf_phys_off)
{
- return (phys_addr_t)(virt - mbuf_phys_off);
+ return (iova_addr_t)(virt - mbuf_phys_off);
}
static inline void
@@ -46,7 +46,7 @@ struct nicvf_rbdr {
uintptr_t rbdr_status;
uintptr_t rbdr_door;
struct rbdr_entry_t *desc;
- nicvf_phys_addr_t phys;
+ nicvf_iova_addr_t phys;
uint32_t buffsz;
uint32_t tail;
uint32_t next_tail;
@@ -56,7 +56,7 @@ struct nicvf_rbdr {
struct nicvf_txq {
union sq_entry_t *desc;
- nicvf_phys_addr_t phys;
+ nicvf_iova_addr_t phys;
struct rte_mbuf **txbuffs;
uintptr_t sq_head;
uintptr_t sq_door;
@@ -87,7 +87,7 @@ struct nicvf_rxq {
uintptr_t cq_status;
uintptr_t cq_door;
union mbuf_initializer mbuf_initializer;
- nicvf_phys_addr_t phys;
+ nicvf_iova_addr_t phys;
union cq_entry_t *desc;
struct nicvf_rbdr *shared_rbdr;
struct nicvf *nic;
@@ -66,7 +66,7 @@ struct virtnet_tx {
struct virtqueue *vq;
/**< memzone to populate hdr. */
const struct rte_memzone *virtio_net_hdr_mz;
- phys_addr_t virtio_net_hdr_mem; /**< hdr for each xmit packet */
+ iova_addr_t virtio_net_hdr_mem; /**< hdr for each xmit packet */
uint16_t queue_id; /**< DPDK queue index. */
uint8_t port_id; /**< Device port identifier. */
@@ -81,7 +81,7 @@ struct virtnet_ctl {
struct virtqueue *vq;
/**< memzone to populate hdr. */
const struct rte_memzone *virtio_net_hdr_mz;
- phys_addr_t virtio_net_hdr_mem; /**< hdr for each xmit packet */
+ iova_addr_t virtio_net_hdr_mem; /**< hdr for each xmit packet */
uint8_t port_id; /**< Device port identifier. */
const struct rte_memzone *mz; /**< mem zone to populate RX ring. */
};
@@ -204,7 +204,7 @@ struct virtqueue {
struct virtnet_ctl cq;
};
- phys_addr_t vq_ring_mem; /**< physical address of vring,
+ iova_addr_t vq_ring_mem; /**< physical address of vring,
* or virtual address for virtio_user. */
/**
@@ -378,7 +378,7 @@ gntalloc_vring_create(int queue_type, uint32_t size, int vtidx)
int pg_size;
uint32_t pg_num;
uint32_t *gref_arr = NULL;
- phys_addr_t *pa_arr = NULL;
+ iova_addr_t *pa_arr = NULL;
uint64_t start_index;
int rv;
@@ -49,7 +49,7 @@
struct _gntarr {
uint32_t gref;
- phys_addr_t pa;
+ iova_addr_t pa;
uint64_t index;
void *va;
};
@@ -58,7 +58,7 @@ struct _mempool_gntalloc_info {
struct rte_mempool *mp;
uint32_t pg_num;
uint32_t *gref_arr;
- phys_addr_t *pa_arr;
+ iova_addr_t *pa_arr;
void *va;
uint32_t mempool_idx;
uint64_t start_index;
@@ -94,7 +94,7 @@ _create_mempool(const char *name, unsigned elt_num, unsigned elt_size,
* gnt_arr: stores all meta dat
*/
uint32_t *gref_arr = NULL;
- phys_addr_t *pa_arr = NULL;
+ iova_addr_t *pa_arr = NULL;
struct _gntarr *gnt_arr = NULL;
/* start index of the grant referances, used for dealloc*/
uint64_t start_index;
@@ -102,7 +102,7 @@ get_xen_virtual(size_t size, size_t page_sz)
* Get the physical address for virtual memory starting at va.
*/
int
-get_phys_map(void *va, phys_addr_t pa[], uint32_t pg_num, uint32_t pg_sz)
+get_phys_map(void *va, iova_addr_t pa[], uint32_t pg_num, uint32_t pg_sz)
{
int32_t fd, rc = 0;
uint32_t i, nb;
@@ -355,7 +355,7 @@ xenstore_write(const char *key_str, const char *val_str)
}
int
-grant_node_create(uint32_t pg_num, uint32_t *gref_arr, phys_addr_t *pa_arr, char *val_str, size_t str_size)
+grant_node_create(uint32_t pg_num, uint32_t *gref_arr, iova_addr_t *pa_arr, char *val_str, size_t str_size)
{
uint64_t start_index;
int pg_size;
@@ -419,7 +419,7 @@ grant_node_create(uint32_t pg_num, uint32_t *gref_arr, phys_addr_t *pa_arr, char
int
-grant_gntalloc_mbuf_pool(struct rte_mempool *mpool, uint32_t pg_num, uint32_t *gref_arr, phys_addr_t *pa_arr, int mempool_idx)
+grant_gntalloc_mbuf_pool(struct rte_mempool *mpool, uint32_t pg_num, uint32_t *gref_arr, iova_addr_t *pa_arr, int mempool_idx)
{
char key_str[PATH_MAX] = {0};
char val_str[PATH_MAX] = {0};
@@ -62,7 +62,7 @@
* Documentation).
*/
#define PAGEMAP_PFN_BITS 54
-#define PAGEMAP_PFN_MASK RTE_LEN2MASK(PAGEMAP_PFN_BITS, phys_addr_t)
+#define PAGEMAP_PFN_MASK RTE_LEN2MASK(PAGEMAP_PFN_BITS, iova_addr_t)
#define MAP_FLAG 0xA5
@@ -99,7 +99,7 @@ int
xenstore_write(const char *key_str, const char *val_str);
int
-get_phys_map(void *va, phys_addr_t pa[], uint32_t pg_num, uint32_t pg_sz);
+get_phys_map(void *va, iova_addr_t pa[], uint32_t pg_num, uint32_t pg_sz);
void *
get_xen_virtual(size_t size, size_t page_sz);
@@ -108,9 +108,9 @@ int
grefwatch_from_alloc(uint32_t *gref, void **pptr);
-int grant_node_create(uint32_t pg_num, uint32_t *gref_arr, phys_addr_t *pa_arr, char *val_str, size_t str_size);
+int grant_node_create(uint32_t pg_num, uint32_t *gref_arr, iova_addr_t *pa_arr, char *val_str, size_t str_size);
int
-grant_gntalloc_mbuf_pool(struct rte_mempool *mpool, uint32_t pg_num, uint32_t *gref_arr, phys_addr_t *pa_arr, int mempool_idx);
+grant_gntalloc_mbuf_pool(struct rte_mempool *mpool, uint32_t pg_num, uint32_t *gref_arr, iova_addr_t *pa_arr, int mempool_idx);
#endif
@@ -139,7 +139,7 @@ enum l2fwd_crypto_xform_chain {
struct l2fwd_key {
uint8_t *data;
uint32_t length;
- phys_addr_t phys_addr;
+ iova_addr_t phys_addr;
};
struct l2fwd_iv {
@@ -117,7 +117,7 @@ struct rte_crypto_op {
struct rte_mempool *mempool;
/**< crypto operation mempool which operation is allocated from */
- phys_addr_t phys_addr;
+ iova_addr_t phys_addr;
/**< physical address of crypto operation */
RTE_STD_C11
@@ -543,7 +543,7 @@ struct rte_crypto_sym_op {
* For GCM (@ref RTE_CRYPTO_AEAD_AES_GCM), for
* "digest result" read "authentication tag T".
*/
- phys_addr_t phys_addr;
+ iova_addr_t phys_addr;
/**< Physical address of digest */
} digest; /**< Digest parameters */
struct {
@@ -579,7 +579,7 @@ struct rte_crypto_sym_op {
* of the block size (16 bytes).
*
*/
- phys_addr_t phys_addr; /**< physical address */
+ iova_addr_t phys_addr; /**< physical address */
} aad;
/**< Additional authentication parameters */
} aead;
@@ -676,7 +676,7 @@ struct rte_crypto_sym_op {
* will overwrite any data at this location.
*
*/
- phys_addr_t phys_addr;
+ iova_addr_t phys_addr;
/**< Physical address of digest */
} digest; /**< Digest parameters */
} auth;
@@ -111,7 +111,7 @@ extern const char **rte_cyptodev_names;
* to calculate address from.
*/
#define rte_crypto_op_ctophys_offset(c, o) \
- (phys_addr_t)((c)->phys_addr + (o))
+ (iova_addr_t)((c)->phys_addr + (o))
/**
* Crypto parameters range description
@@ -50,7 +50,7 @@
/*
* Get physical address of any mapped virtual address in the current process.
*/
-phys_addr_t
+iova_addr_t
rte_mem_virt2phy(const void *virtaddr)
{
/* XXX not implemented. This function is only used by
@@ -73,7 +73,7 @@ rte_eal_hugepage_init(void)
/* for debug purposes, hugetlbfs can be disabled */
if (internal_config.no_hugetlbfs) {
addr = malloc(internal_config.memory);
- mcfg->memseg[0].phys_addr = (phys_addr_t)(uintptr_t)addr;
+ mcfg->memseg[0].phys_addr = (iova_addr_t)(uintptr_t)addr;
mcfg->memseg[0].addr = addr;
mcfg->memseg[0].hugepage_sz = RTE_PGSIZE_4K;
mcfg->memseg[0].len = internal_config.memory;
@@ -332,7 +332,7 @@ rte_malloc_set_limit(const char *type, size_t max);
* RTE_BAD_PHYS_ADDR on error
* otherwise return physical address of the buffer
*/
-phys_addr_t
+iova_addr_t
rte_malloc_virt2phy(const void *addr);
#ifdef __cplusplus
@@ -98,14 +98,14 @@ enum rte_page_sizes {
*/
#define __rte_cache_min_aligned __rte_aligned(RTE_CACHE_LINE_MIN_SIZE)
-typedef uint64_t phys_addr_t; /**< Physical address definition. */
-#define RTE_BAD_PHYS_ADDR ((phys_addr_t)-1)
+typedef uint64_t iova_addr_t; /**< Physical address definition. */
+#define RTE_BAD_PHYS_ADDR ((iova_addr_t)-1)
/**
* Physical memory segment descriptor.
*/
struct rte_memseg {
- phys_addr_t phys_addr; /**< Start physical address. */
+ iova_addr_t phys_addr; /**< Start physical address. */
RTE_STD_C11
union {
void *addr; /**< Start virtual address. */
@@ -142,7 +142,7 @@ int rte_mem_lock_page(const void *virt);
* @return
* The physical address or RTE_BAD_PHYS_ADDR on error.
*/
-phys_addr_t rte_mem_virt2phy(const void *virt);
+iova_addr_t rte_mem_virt2phy(const void *virt);
/**
* Get the layout of the available physical memory.
@@ -201,7 +201,7 @@ unsigned rte_memory_get_nrank(void);
int rte_xen_dom0_supported(void);
/**< Internal use only - phys to virt mapping for xen */
-phys_addr_t rte_xen_mem_phy2mch(int32_t, const phys_addr_t);
+iova_addr_t rte_xen_mem_phy2mch(int32_t, const iova_addr_t);
/**
* Return the physical address of elt, which is an element of the pool mp.
@@ -215,8 +215,8 @@ phys_addr_t rte_xen_mem_phy2mch(int32_t, const phys_addr_t);
* @return
* The physical address or RTE_BAD_PHYS_ADDR on error.
*/
-static inline phys_addr_t
-rte_mem_phy2mch(int32_t memseg_id, const phys_addr_t phy_addr)
+static inline iova_addr_t
+rte_mem_phy2mch(int32_t memseg_id, const iova_addr_t phy_addr)
{
if (rte_xen_dom0_supported())
return rte_xen_mem_phy2mch(memseg_id, phy_addr);
@@ -251,8 +251,8 @@ static inline int rte_xen_dom0_supported(void)
return 0;
}
-static inline phys_addr_t
-rte_mem_phy2mch(int32_t memseg_id __rte_unused, const phys_addr_t phy_addr)
+static inline iova_addr_t
+rte_mem_phy2mch(int32_t memseg_id __rte_unused, const iova_addr_t phy_addr)
{
return phy_addr;
}
@@ -78,7 +78,7 @@ struct rte_memzone {
#define RTE_MEMZONE_NAMESIZE 32 /**< Maximum length of memory zone name.*/
char name[RTE_MEMZONE_NAMESIZE]; /**< Name of the memory zone. */
- phys_addr_t phys_addr; /**< Start physical address. */
+ iova_addr_t phys_addr; /**< Start physical address. */
RTE_STD_C11
union {
void *addr; /**< Start virtual address. */
@@ -248,7 +248,7 @@ rte_malloc_set_limit(__rte_unused const char *type,
/*
* Return the physical address of a virtual address obtained through rte_malloc
*/
-phys_addr_t
+iova_addr_t
rte_malloc_virt2phy(const void *addr)
{
const struct malloc_elem *elem = malloc_elem_from_data(addr);
@@ -104,7 +104,7 @@ static void
test_phys_addrs_available(void)
{
uint64_t tmp;
- phys_addr_t physaddr;
+ iova_addr_t physaddr;
/* For dom0, phys addresses can always be available */
if (rte_xen_dom0_supported())
@@ -130,7 +130,7 @@ test_phys_addrs_available(void)
/*
* Get physical address of any mapped virtual address in the current process.
*/
-phys_addr_t
+iova_addr_t
rte_mem_virt2phy(const void *virtaddr)
{
int fd, retval;
@@ -219,7 +219,7 @@ static int
find_physaddrs(struct hugepage_file *hugepg_tbl, struct hugepage_info *hpi)
{
unsigned int i;
- phys_addr_t addr;
+ iova_addr_t addr;
for (i = 0; i < hpi->num_pages[0]; i++) {
addr = rte_mem_virt2phy(hugepg_tbl[i].orig_va);
@@ -237,7 +237,7 @@ static int
set_physaddrs(struct hugepage_file *hugepg_tbl, struct hugepage_info *hpi)
{
unsigned int i;
- static phys_addr_t addr;
+ static iova_addr_t addr;
for (i = 0; i < hpi->num_pages[0]; i++) {
hugepg_tbl[i].physaddr = addr;
@@ -153,8 +153,8 @@ get_xen_memory_size(void)
/**
* Based on physical address to caculate MFN in Xen Dom0.
*/
-phys_addr_t
-rte_xen_mem_phy2mch(int32_t memseg_id, const phys_addr_t phy_addr)
+iova_addr_t
+rte_xen_mem_phy2mch(int32_t memseg_id, const iova_addr_t phy_addr)
{
int mfn_id, i;
uint64_t mfn, mfn_offset;
@@ -73,6 +73,10 @@
#define RTE_CACHE_LINE_MIN_SIZE 64
+#ifdef __KERNEL__
+typedef uint64_t iova_addr_t;
+#endif
+
/*
* Request id.
*/
@@ -138,20 +142,20 @@ struct rte_kni_mbuf {
struct rte_kni_device_info {
char name[RTE_KNI_NAMESIZE]; /**< Network device name for KNI */
- phys_addr_t tx_phys;
- phys_addr_t rx_phys;
- phys_addr_t alloc_phys;
- phys_addr_t free_phys;
+ iova_addr_t tx_phys;
+ iova_addr_t rx_phys;
+ iova_addr_t alloc_phys;
+ iova_addr_t free_phys;
/* Used by Ethtool */
- phys_addr_t req_phys;
- phys_addr_t resp_phys;
- phys_addr_t sync_phys;
+ iova_addr_t req_phys;
+ iova_addr_t resp_phys;
+ iova_addr_t sync_phys;
void * sync_va;
/* mbuf mempool */
void * mbuf_va;
- phys_addr_t mbuf_phys;
+ iova_addr_t mbuf_phys;
/* PCI info */
uint16_t vendor_id; /**< Vendor ID or PCI_ANY_ID. */
@@ -411,7 +411,7 @@ struct rte_mbuf {
* same mbuf cacheline0 layout for 32-bit and 64-bit. This makes
* working on vector drivers easier.
*/
- phys_addr_t buf_physaddr __rte_aligned(sizeof(phys_addr_t));
+ iova_addr_t buf_physaddr __rte_aligned(sizeof(iova_addr_t));
/* next 8 bytes are initialised on RX descriptor rearm */
MARKER64 rearm_data;
@@ -594,7 +594,7 @@ static inline uint16_t rte_pktmbuf_priv_size(struct rte_mempool *mp);
* @return
* The physical address of the beginning of the mbuf data
*/
-static inline phys_addr_t
+static inline iova_addr_t
rte_mbuf_data_dma_addr(const struct rte_mbuf *mb)
{
return mb->buf_physaddr + mb->data_off;
@@ -612,7 +612,7 @@ rte_mbuf_data_dma_addr(const struct rte_mbuf *mb)
* @return
* The physical address of the beginning of the mbuf data
*/
-static inline phys_addr_t
+static inline iova_addr_t
rte_mbuf_data_dma_addr_default(const struct rte_mbuf *mb)
{
return mb->buf_physaddr + RTE_PKTMBUF_HEADROOM;
@@ -1533,7 +1533,7 @@ static inline struct rte_mbuf *rte_pktmbuf_lastseg(struct rte_mbuf *m)
* The offset into the data to calculate address from.
*/
#define rte_pktmbuf_mtophys_offset(m, o) \
- (phys_addr_t)((m)->buf_physaddr + (m)->data_off + (o))
+ (iova_addr_t)((m)->buf_physaddr + (m)->data_off + (o))
/**
* A macro that returns the physical address that points to the start of the
@@ -128,7 +128,7 @@ static unsigned optimize_object_size(unsigned obj_size)
}
static void
-mempool_add_elem(struct rte_mempool *mp, void *obj, phys_addr_t physaddr)
+mempool_add_elem(struct rte_mempool *mp, void *obj, iova_addr_t physaddr)
{
struct rte_mempool_objhdr *hdr;
struct rte_mempool_objtlr *tlr __rte_unused;
@@ -263,11 +263,11 @@ rte_mempool_xmem_size(uint32_t elt_num, size_t total_elt_sz, uint32_t pg_shift)
*/
ssize_t
rte_mempool_xmem_usage(__rte_unused void *vaddr, uint32_t elt_num,
- size_t total_elt_sz, const phys_addr_t paddr[], uint32_t pg_num,
+ size_t total_elt_sz, const iova_addr_t paddr[], uint32_t pg_num,
uint32_t pg_shift)
{
uint32_t elt_cnt = 0;
- phys_addr_t start, end;
+ iova_addr_t start, end;
uint32_t paddr_idx;
size_t pg_sz = (size_t)1 << pg_shift;
@@ -345,7 +345,7 @@ rte_mempool_free_memchunks(struct rte_mempool *mp)
*/
int
rte_mempool_populate_phys(struct rte_mempool *mp, char *vaddr,
- phys_addr_t paddr, size_t len, rte_mempool_memchunk_free_cb_t *free_cb,
+ iova_addr_t paddr, size_t len, rte_mempool_memchunk_free_cb_t *free_cb,
void *opaque)
{
unsigned total_elt_sz;
@@ -409,7 +409,7 @@ rte_mempool_populate_phys(struct rte_mempool *mp, char *vaddr,
*/
int
rte_mempool_populate_phys_tab(struct rte_mempool *mp, char *vaddr,
- const phys_addr_t paddr[], uint32_t pg_num, uint32_t pg_shift,
+ const iova_addr_t paddr[], uint32_t pg_num, uint32_t pg_shift,
rte_mempool_memchunk_free_cb_t *free_cb, void *opaque)
{
uint32_t i, n;
@@ -452,7 +452,7 @@ rte_mempool_populate_virt(struct rte_mempool *mp, char *addr,
size_t len, size_t pg_sz, rte_mempool_memchunk_free_cb_t *free_cb,
void *opaque)
{
- phys_addr_t paddr;
+ iova_addr_t paddr;
size_t off, phys_len;
int ret, cnt = 0;
@@ -483,7 +483,7 @@ rte_mempool_populate_virt(struct rte_mempool *mp, char *addr,
/* populate with the largest group of contiguous pages */
for (phys_len = pg_sz; off + phys_len < len; phys_len += pg_sz) {
- phys_addr_t paddr_tmp;
+ iova_addr_t paddr_tmp;
paddr_tmp = rte_mem_virt2phy(addr + off + phys_len);
paddr_tmp = rte_mem_phy2mch(-1, paddr_tmp);
@@ -519,7 +519,7 @@ rte_mempool_populate_default(struct rte_mempool *mp)
char mz_name[RTE_MEMZONE_NAMESIZE];
const struct rte_memzone *mz;
size_t size, total_elt_sz, align, pg_sz, pg_shift;
- phys_addr_t paddr;
+ iova_addr_t paddr;
unsigned mz_id, n;
int ret;
@@ -922,7 +922,7 @@ rte_mempool_xmem_create(const char *name, unsigned n, unsigned elt_size,
rte_mempool_ctor_t *mp_init, void *mp_init_arg,
rte_mempool_obj_cb_t *obj_init, void *obj_init_arg,
int socket_id, unsigned flags, void *vaddr,
- const phys_addr_t paddr[], uint32_t pg_num, uint32_t pg_shift)
+ const iova_addr_t paddr[], uint32_t pg_num, uint32_t pg_shift)
{
struct rte_mempool *mp = NULL;
int ret;
@@ -157,7 +157,7 @@ struct rte_mempool_objsz {
struct rte_mempool_objhdr {
STAILQ_ENTRY(rte_mempool_objhdr) next; /**< Next in list. */
struct rte_mempool *mp; /**< The mempool owning the object. */
- phys_addr_t physaddr; /**< Physical address of the object. */
+ iova_addr_t physaddr; /**< Physical address of the object. */
#ifdef RTE_LIBRTE_MEMPOOL_DEBUG
uint64_t cookie; /**< Debug cookie. */
#endif
@@ -203,7 +203,7 @@ struct rte_mempool_memhdr {
STAILQ_ENTRY(rte_mempool_memhdr) next; /**< Next in list. */
struct rte_mempool *mp; /**< The mempool owning the chunk */
void *addr; /**< Virtual address of the chunk */
- phys_addr_t phys_addr; /**< Physical address of the chunk */
+ iova_addr_t phys_addr; /**< Physical address of the chunk */
size_t len; /**< length of the chunk */
rte_mempool_memchunk_free_cb_t *free_cb; /**< Free callback */
void *opaque; /**< Argument passed to the free callback */
@@ -739,7 +739,7 @@ rte_mempool_xmem_create(const char *name, unsigned n, unsigned elt_size,
rte_mempool_ctor_t *mp_init, void *mp_init_arg,
rte_mempool_obj_cb_t *obj_init, void *obj_init_arg,
int socket_id, unsigned flags, void *vaddr,
- const phys_addr_t paddr[], uint32_t pg_num, uint32_t pg_shift);
+ const iova_addr_t paddr[], uint32_t pg_num, uint32_t pg_shift);
/**
* Create an empty mempool
@@ -820,7 +820,7 @@ rte_mempool_free(struct rte_mempool *mp);
* mempool and a negative errno is returned.
*/
int rte_mempool_populate_phys(struct rte_mempool *mp, char *vaddr,
- phys_addr_t paddr, size_t len, rte_mempool_memchunk_free_cb_t *free_cb,
+ iova_addr_t paddr, size_t len, rte_mempool_memchunk_free_cb_t *free_cb,
void *opaque);
/**
@@ -851,7 +851,7 @@ int rte_mempool_populate_phys(struct rte_mempool *mp, char *vaddr,
* mempool and a negative errno is returned.
*/
int rte_mempool_populate_phys_tab(struct rte_mempool *mp, char *vaddr,
- const phys_addr_t paddr[], uint32_t pg_num, uint32_t pg_shift,
+ const iova_addr_t paddr[], uint32_t pg_num, uint32_t pg_shift,
rte_mempool_memchunk_free_cb_t *free_cb, void *opaque);
/**
@@ -1394,7 +1394,7 @@ rte_mempool_empty(const struct rte_mempool *mp)
* If the mempool was created with MEMPOOL_F_NO_PHYS_CONTIG, the
* returned value is RTE_BAD_PHYS_ADDR.
*/
-static inline phys_addr_t
+static inline iova_addr_t
rte_mempool_virt2phy(__rte_unused const struct rte_mempool *mp, const void *elt)
{
const struct rte_mempool_objhdr *hdr;
@@ -1523,7 +1523,7 @@ size_t rte_mempool_xmem_size(uint32_t elt_num, size_t total_elt_sz,
* is the actual number of elements that can be stored in that buffer.
*/
ssize_t rte_mempool_xmem_usage(void *vaddr, uint32_t elt_num,
- size_t total_elt_sz, const phys_addr_t paddr[], uint32_t pg_num,
+ size_t total_elt_sz, const iova_addr_t paddr[], uint32_t pg_num,
uint32_t pg_shift);
/**
@@ -281,7 +281,7 @@ extern uint64_t VHOST_FEATURES;
extern struct virtio_net *vhost_devices[MAX_VHOST_DEVICE];
/* Convert guest physical address to host physical address */
-static __rte_always_inline phys_addr_t
+static __rte_always_inline iova_addr_t
gpa_to_hpa(struct virtio_net *dev, uint64_t gpa, uint64_t size)
{
uint32_t i;
@@ -152,7 +152,7 @@ pktmbuf_mtod_offset(struct rte_mbuf *mbuf, int offset) {
return rte_pktmbuf_mtod_offset(m, uint8_t *, offset);
}
-static inline phys_addr_t
+static inline iova_addr_t
pktmbuf_mtophys_offset(struct rte_mbuf *mbuf, int offset) {
struct rte_mbuf *m;
@@ -78,7 +78,7 @@
/* Test if memory overlaps: return 1 if true, or 0 if false. */
static int
-is_memory_overlap(phys_addr_t ptr1, size_t len1, phys_addr_t ptr2, size_t len2)
+is_memory_overlap(iova_addr_t ptr1, size_t len1, iova_addr_t ptr2, size_t len2)
{
if (ptr2 >= ptr1 && (ptr2 - ptr1) < len1)
return 1;
@@ -601,9 +601,9 @@ check_memzone_bounded(const char *name, uint32_t len, uint32_t align,
uint32_t bound)
{
const struct rte_memzone *mz;
- phys_addr_t bmask;
+ iova_addr_t bmask;
- bmask = ~((phys_addr_t)bound - 1);
+ bmask = ~((iova_addr_t)bound - 1);
if ((mz = rte_memzone_reserve_bounded(name, len, SOCKET_ID_ANY, 0,
align, bound)) == NULL) {
@@ -612,7 +612,7 @@ check_memzone_bounded(const char *name, uint32_t len, uint32_t align,
return -1;
}
- if ((mz->phys_addr & ((phys_addr_t)align - 1)) != 0) {
+ if ((mz->phys_addr & ((iova_addr_t)align - 1)) != 0) {
printf("%s(%s): invalid phys addr alignment\n",
__func__, mz->name);
return -1;