[dpdk-dev,v2,2/2] net/ixgbe : backplane port MDIO support

  From: Shweta Choudaha <shweta.choudaha@att.com>

Initialize MDIO read/write functions for backplan port
(IXGBE_DEV_ID_X550EM_A_KR_L) to enable read/write
registers via MDIO

Signed-off-by: Shweta Choudaha <shweta.choudaha@att.com>
Reviewed-by: Chas Williams <chas3@att.com>
Reviewed-by: Luca Boccassi <bluca@debian.org>
---
 drivers/net/ixgbe/base/ixgbe_x550.c | 1 +
 1 file changed, 1 insertion(+)
  

> -----Original Message-----
> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Shweta Choudaha
> Sent: Monday, November 6, 2017 10:25 PM
> To: dev@dpdk.org
> Cc: Shweta Choudaha
> Subject: [dpdk-dev] [PATCH v2 2/2] net/ixgbe : backplane port MDIO support
> 
> From: Shweta Choudaha <shweta.choudaha@att.com>
> 
> Initialize MDIO read/write functions for backplan port
> (IXGBE_DEV_ID_X550EM_A_KR_L) to enable read/write registers via MDIO
> 
> Signed-off-by: Shweta Choudaha <shweta.choudaha@att.com>
> Reviewed-by: Chas Williams <chas3@att.com>
> Reviewed-by: Luca Boccassi <bluca@debian.org>
> ---
>  drivers/net/ixgbe/base/ixgbe_x550.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/net/ixgbe/base/ixgbe_x550.c
> b/drivers/net/ixgbe/base/ixgbe_x550.c
> index 9862391..3f89dc4 100644
> --- a/drivers/net/ixgbe/base/ixgbe_x550.c
> +++ b/drivers/net/ixgbe/base/ixgbe_x550.c
> @@ -2374,6 +2374,7 @@ s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw
> *hw)
>  	}
> 
>  	switch (hw->device_id) {
> +	case IXGBE_DEV_ID_X550EM_A_KR_L:
Basically the source files in 'base' folder is handled by Intel, I will check if this
code change is acceptable by some internal stakeholders. I will let you know later.

Thanks,
Helin
>  	case IXGBE_DEV_ID_X550EM_A_1G_T:
>  	case IXGBE_DEV_ID_X550EM_A_1G_T_L:
>  		phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
> --
> 2.1.4
  

> -----Original Message-----
> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Shweta Choudaha
> Sent: Monday, November 6, 2017 10:25 PM
> To: dev@dpdk.org
> Cc: Shweta Choudaha
> Subject: [dpdk-dev] [PATCH v2 2/2] net/ixgbe : backplane port MDIO support
> 
> From: Shweta Choudaha <shweta.choudaha@att.com>
> 
> Initialize MDIO read/write functions for backplan port
> (IXGBE_DEV_ID_X550EM_A_KR_L) to enable read/write registers via MDIO
> 
> Signed-off-by: Shweta Choudaha <shweta.choudaha@att.com>
> Reviewed-by: Chas Williams <chas3@att.com>
> Reviewed-by: Luca Boccassi <bluca@debian.org>
> ---
>  drivers/net/ixgbe/base/ixgbe_x550.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/net/ixgbe/base/ixgbe_x550.c
> b/drivers/net/ixgbe/base/ixgbe_x550.c
> index 9862391..3f89dc4 100644
> --- a/drivers/net/ixgbe/base/ixgbe_x550.c
> +++ b/drivers/net/ixgbe/base/ixgbe_x550.c
> @@ -2374,6 +2374,7 @@ s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw
> *hw)
>  	}
> 
>  	switch (hw->device_id) {
> +	case IXGBE_DEV_ID_X550EM_A_KR_L:
Basically this device ID is for a specific SoC platform, there is no external PHY for it.
We prefer to NACK it. I added more experts here to answer more questions if you have.
Note that they are not working on DPDK, and they are experts on ixgbe NIC/SW.
Or we can discuss more if you have any requests to Intel.

Sorry,
Helin

>  	case IXGBE_DEV_ID_X550EM_A_1G_T:
>  	case IXGBE_DEV_ID_X550EM_A_1G_T_L:
>  		phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
> --
> 2.1.4
  

Hi Helin,

  Thanks for the review.
Yes , the backplane interfaces(x550em) does not have a phy connected
but it still MDIO lines for control. The requirement for us is to be able
to access
phy registers over backplane MDIO . I 've an updated patchset which is
cleaner.
I 'll send that for review.

Thanks,
Shweta


On Wed, Jan 10, 2018 at 3:17 AM, Zhang, Helin <helin.zhang@intel.com> wrote:

>
>
> > -----Original Message-----
> > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Shweta Choudaha
> > Sent: Monday, November 6, 2017 10:25 PM
> > To: dev@dpdk.org
> > Cc: Shweta Choudaha
> > Subject: [dpdk-dev] [PATCH v2 2/2] net/ixgbe : backplane port MDIO
> support
> >
> > From: Shweta Choudaha <shweta.choudaha@att.com>
> >
> > Initialize MDIO read/write functions for backplan port
> > (IXGBE_DEV_ID_X550EM_A_KR_L) to enable read/write registers via MDIO
> >
> > Signed-off-by: Shweta Choudaha <shweta.choudaha@att.com>
> > Reviewed-by: Chas Williams <chas3@att.com>
> > Reviewed-by: Luca Boccassi <bluca@debian.org>
> > ---
> >  drivers/net/ixgbe/base/ixgbe_x550.c | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/net/ixgbe/base/ixgbe_x550.c
> > b/drivers/net/ixgbe/base/ixgbe_x550.c
> > index 9862391..3f89dc4 100644
> > --- a/drivers/net/ixgbe/base/ixgbe_x550.c
> > +++ b/drivers/net/ixgbe/base/ixgbe_x550.c
> > @@ -2374,6 +2374,7 @@ s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw
> > *hw)
> >       }
> >
> >       switch (hw->device_id) {
> > +     case IXGBE_DEV_ID_X550EM_A_KR_L:
> Basically this device ID is for a specific SoC platform, there is no
> external PHY for it.
> We prefer to NACK it. I added more experts here to answer more questions
> if you have.
> Note that they are not working on DPDK, and they are experts on ixgbe
> NIC/SW.
> Or we can discuss more if you have any requests to Intel.
>
> Sorry,
> Helin
>
> >       case IXGBE_DEV_ID_X550EM_A_1G_T:
> >       case IXGBE_DEV_ID_X550EM_A_1G_T_L:
> >               phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
> > --
> > 2.1.4
>
>