[dpdk-dev] [PATCH 03/22] i40e: add i40e support
Helin Zhang
helin.zhang at intel.com
Wed May 21 17:30:02 CEST 2014
Add i40e support by modifying neccessary source files.
The componets modified are,
- Add configurations for i40e in config/
- Modified neccessary makefiles in both k/ and lib/
- Modified neccessary source files in librte_ether/
- Add more packet bit flags in rte_mbuf.h
- Add i40e support in igb_uio
- Add i40e support in rte_pci_dev_ids.h, including new device IDs
Signed-off-by: Helin Zhang <helin.zhang at intel.com>
Signed-off-by: Mark Chen <jing.d.chen at intel.com>
---
config/defconfig_i686-default-linuxapp-gcc | 20 ++++
config/defconfig_i686-default-linuxapp-icc | 20 ++++
config/defconfig_x86_64-default-bsdapp-gcc | 15 +++
config/defconfig_x86_64-default-linuxapp-gcc | 20 ++++
config/defconfig_x86_64-default-linuxapp-icc | 20 ++++
lib/Makefile | 1 +
lib/librte_eal/common/include/rte_pci_dev_ids.h | 44 +++++++
lib/librte_eal/linuxapp/igb_uio/igb_uio.c | 2 +
lib/librte_ether/rte_ethdev.c | 15 +++
lib/librte_ether/rte_ethdev.h | 146 +++++++++++++++++++++---
lib/librte_ether/rte_ether.h | 24 ++++
lib/librte_mbuf/rte_mbuf.h | 8 ++
mk/rte.app.mk | 4 +
13 files changed, 323 insertions(+), 16 deletions(-)
diff --git a/config/defconfig_i686-default-linuxapp-gcc b/config/defconfig_i686-default-linuxapp-gcc
index 14bd3d1..931f6c5 100644
--- a/config/defconfig_i686-default-linuxapp-gcc
+++ b/config/defconfig_i686-default-linuxapp-gcc
@@ -179,6 +179,26 @@ CONFIG_RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC=y
CONFIG_RTE_LIBRTE_IXGBE_ALLOW_UNSUPPORTED_SFP=n
#
+# Compile burst-oriented I40E PMD driver
+#
+# CONFIG_RTE_LIBRTE_I40E_ITR_INTERVAL can be 0 to 8160 us,
+# otherwise a default value will be used instead.
+# The interval will be aligned to 2, due to the hardware restriction.
+#
+CONFIG_RTE_LIBRTE_I40E_PMD=y
+CONFIG_RTE_LIBRTE_I40E_DEBUG_INIT=n
+CONFIG_RTE_LIBRTE_I40E_DEBUG_RX=n
+CONFIG_RTE_LIBRTE_I40E_DEBUG_TX=n
+CONFIG_RTE_LIBRTE_I40E_DEBUG_TX_FREE=n
+CONFIG_RTE_LIBRTE_I40E_DEBUG_DRIVER=n
+CONFIG_RTE_LIBRTE_I40E_PF_DISABLE_STRIP_CRC=n
+CONFIG_RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC=y
+CONFIG_RTE_LIBRTE_I40E_ALLOW_UNSUPPORTED_SFP=n
+CONFIG_RTE_LIBRTE_I40E_16BYTE_RX_DESC=n
+CONFIG_RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF=4
+CONFIG_RTE_LIBRTE_I40E_ITR_INTERVAL=-1
+
+#
# Compile burst-oriented VIRTIO PMD driver
#
CONFIG_RTE_LIBRTE_VIRTIO_PMD=y
diff --git a/config/defconfig_i686-default-linuxapp-icc b/config/defconfig_i686-default-linuxapp-icc
index ec3386e..b07bd76 100644
--- a/config/defconfig_i686-default-linuxapp-icc
+++ b/config/defconfig_i686-default-linuxapp-icc
@@ -179,6 +179,26 @@ CONFIG_RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC=y
CONFIG_RTE_LIBRTE_IXGBE_ALLOW_UNSUPPORTED_SFP=n
#
+# Compile burst-oriented I40E PMD driver
+#
+# CONFIG_RTE_LIBRTE_I40E_ITR_INTERVAL can be 0 to 8160 us,
+# otherwise a default value will be used instead.
+# The interval will be aligned to 2, due to the hardware restriction.
+#
+CONFIG_RTE_LIBRTE_I40E_PMD=y
+CONFIG_RTE_LIBRTE_I40E_DEBUG_INIT=n
+CONFIG_RTE_LIBRTE_I40E_DEBUG_RX=n
+CONFIG_RTE_LIBRTE_I40E_DEBUG_TX=n
+CONFIG_RTE_LIBRTE_I40E_DEBUG_TX_FREE=n
+CONFIG_RTE_LIBRTE_I40E_DEBUG_DRIVER=n
+CONFIG_RTE_LIBRTE_I40E_PF_DISABLE_STRIP_CRC=n
+CONFIG_RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC=y
+CONFIG_RTE_LIBRTE_I40E_ALLOW_UNSUPPORTED_SFP=n
+CONFIG_RTE_LIBRTE_I40E_16BYTE_RX_DESC=n
+CONFIG_RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF=4
+CONFIG_RTE_LIBRTE_I40E_ITR_INTERVAL=-1
+
+#
# Compile burst-oriented VIRTIO PMD driver
#
CONFIG_RTE_LIBRTE_VIRTIO_PMD=y
diff --git a/config/defconfig_x86_64-default-bsdapp-gcc b/config/defconfig_x86_64-default-bsdapp-gcc
index d960e1d..b03bc98 100644
--- a/config/defconfig_x86_64-default-bsdapp-gcc
+++ b/config/defconfig_x86_64-default-bsdapp-gcc
@@ -165,6 +165,21 @@ CONFIG_RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC=y
CONFIG_RTE_LIBRTE_IXGBE_ALLOW_UNSUPPORTED_SFP=n
#
+# Compile burst-oriented I40E PMD driver
+#
+CONFIG_RTE_LIBRTE_I40E_PMD=y
+CONFIG_RTE_LIBRTE_I40E_DEBUG_INIT=y
+CONFIG_RTE_LIBRTE_I40E_DEBUG_RX=y
+CONFIG_RTE_LIBRTE_I40E_DEBUG_TX=y
+CONFIG_RTE_LIBRTE_I40E_DEBUG_TX_FREE=y
+CONFIG_RTE_LIBRTE_I40E_DEBUG_DRIVER=y
+CONFIG_RTE_LIBRTE_I40E_PF_DISABLE_STRIP_CRC=y
+CONFIG_RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC=n
+CONFIG_RTE_LIBRTE_I40E_ALLOW_UNSUPPORTED_SFP=y
+CONFIG_RTE_LIBRTE_I40E_16BYTE_RX_DESC=n
+CONFIG_RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF=4
+
+#
# Compile burst-oriented VIRTIO PMD driver
#
CONFIG_RTE_LIBRTE_VIRTIO_PMD=n
diff --git a/config/defconfig_x86_64-default-linuxapp-gcc b/config/defconfig_x86_64-default-linuxapp-gcc
index f11ffbf..b8ccb2f 100644
--- a/config/defconfig_x86_64-default-linuxapp-gcc
+++ b/config/defconfig_x86_64-default-linuxapp-gcc
@@ -179,6 +179,26 @@ CONFIG_RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC=y
CONFIG_RTE_LIBRTE_IXGBE_ALLOW_UNSUPPORTED_SFP=n
#
+# Compile burst-oriented I40E PMD driver
+#
+# CONFIG_RTE_LIBRTE_I40E_ITR_INTERVAL can be 0 to 8160 us,
+# otherwise a default value will be used instead.
+# The interval will be aligned to 2, due to the hardware restriction.
+#
+CONFIG_RTE_LIBRTE_I40E_PMD=y
+CONFIG_RTE_LIBRTE_I40E_DEBUG_INIT=n
+CONFIG_RTE_LIBRTE_I40E_DEBUG_RX=n
+CONFIG_RTE_LIBRTE_I40E_DEBUG_TX=n
+CONFIG_RTE_LIBRTE_I40E_DEBUG_TX_FREE=n
+CONFIG_RTE_LIBRTE_I40E_DEBUG_DRIVER=n
+CONFIG_RTE_LIBRTE_I40E_PF_DISABLE_STRIP_CRC=n
+CONFIG_RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC=y
+CONFIG_RTE_LIBRTE_I40E_ALLOW_UNSUPPORTED_SFP=n
+CONFIG_RTE_LIBRTE_I40E_16BYTE_RX_DESC=n
+CONFIG_RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF=4
+CONFIG_RTE_LIBRTE_I40E_ITR_INTERVAL=-1
+
+#
# Compile burst-oriented VIRTIO PMD driver
#
CONFIG_RTE_LIBRTE_VIRTIO_PMD=y
diff --git a/config/defconfig_x86_64-default-linuxapp-icc b/config/defconfig_x86_64-default-linuxapp-icc
index 4eaca4c..58a6c62 100644
--- a/config/defconfig_x86_64-default-linuxapp-icc
+++ b/config/defconfig_x86_64-default-linuxapp-icc
@@ -179,6 +179,26 @@ CONFIG_RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC=y
CONFIG_RTE_LIBRTE_IXGBE_ALLOW_UNSUPPORTED_SFP=n
#
+# Compile burst-oriented I40E PMD driver
+#
+# CONFIG_RTE_LIBRTE_I40E_ITR_INTERVAL can be 0 to 8160 us,
+# otherwise a default value will be used instead.
+# The interval will be aligned to 2, due to the hardware restriction.
+#
+CONFIG_RTE_LIBRTE_I40E_PMD=y
+CONFIG_RTE_LIBRTE_I40E_DEBUG_INIT=n
+CONFIG_RTE_LIBRTE_I40E_DEBUG_RX=n
+CONFIG_RTE_LIBRTE_I40E_DEBUG_TX=n
+CONFIG_RTE_LIBRTE_I40E_DEBUG_TX_FREE=n
+CONFIG_RTE_LIBRTE_I40E_DEBUG_DRIVER=n
+CONFIG_RTE_LIBRTE_I40E_PF_DISABLE_STRIP_CRC=n
+CONFIG_RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC=y
+CONFIG_RTE_LIBRTE_I40E_ALLOW_UNSUPPORTED_SFP=n
+CONFIG_RTE_LIBRTE_I40E_16BYTE_RX_DESC=n
+CONFIG_RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF=4
+CONFIG_RTE_LIBRTE_I40E_ITR_INTERVAL=-1
+
+#
# Compile burst-oriented VIRTIO PMD driver
#
CONFIG_RTE_LIBRTE_VIRTIO_PMD=y
diff --git a/lib/Makefile b/lib/Makefile
index b92b392..e5b6635 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -42,6 +42,7 @@ DIRS-$(CONFIG_RTE_LIBRTE_CMDLINE) += librte_cmdline
DIRS-$(CONFIG_RTE_LIBRTE_ETHER) += librte_ether
DIRS-$(CONFIG_RTE_LIBRTE_E1000_PMD) += librte_pmd_e1000
DIRS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += librte_pmd_ixgbe
+DIRS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += librte_pmd_i40e
DIRS-$(CONFIG_RTE_LIBRTE_PMD_RING) += librte_pmd_ring
DIRS-$(CONFIG_RTE_LIBRTE_PMD_PCAP) += librte_pmd_pcap
DIRS-$(CONFIG_RTE_LIBRTE_VIRTIO_PMD) += librte_pmd_virtio
diff --git a/lib/librte_eal/common/include/rte_pci_dev_ids.h b/lib/librte_eal/common/include/rte_pci_dev_ids.h
index a51c1ef..f89b0e8 100644
--- a/lib/librte_eal/common/include/rte_pci_dev_ids.h
+++ b/lib/librte_eal/common/include/rte_pci_dev_ids.h
@@ -73,6 +73,8 @@
* RTE_PCI_DEV_ID_DECL_IGBVF
* RTE_PCI_DEV_ID_DECL_IXGBE
* RTE_PCI_DEV_ID_DECL_IXGBEVF
+ * RTE_PCI_DEV_ID_DECL_I40E
+ * RTE_PCI_DEV_ID_DECL_I40EVF
* RTE_PCI_DEV_ID_DECL_VIRTIO
* at the time when this file is included.
*
@@ -114,6 +116,14 @@
#define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev)
#endif
+#ifndef RTE_PCI_DEV_ID_DECL_I40E
+#define RTE_PCI_DEV_ID_DECL_I40E(vend, dev)
+#endif
+
+#ifndef RTE_PCI_DEV_ID_DECL_I40EVF
+#define RTE_PCI_DEV_ID_DECL_I40EVF(vend, dev)
+#endif
+
#ifndef RTE_PCI_DEV_ID_DECL_VIRTIO
#define RTE_PCI_DEV_ID_DECL_VIRTIO(vend, dev)
#endif
@@ -444,6 +454,30 @@ RTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_X540T1)
RTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82599_BYPASS)
#endif
+/*************** Physical I40E devices from i40e_type.h *****************/
+
+#define I40E_DEV_ID_SFP_XL710 0x1572
+#define I40E_DEV_ID_SFP_X710 0x1573
+#define I40E_DEV_ID_QEMU 0x1574
+#define I40E_DEV_ID_KX_A 0x157F
+#define I40E_DEV_ID_KX_B 0x1580
+#define I40E_DEV_ID_KX_C 0x1581
+#define I40E_DEV_ID_KX_D 0x1582
+#define I40E_DEV_ID_QSFP_A 0x1583
+#define I40E_DEV_ID_QSFP_B 0x1584
+#define I40E_DEV_ID_QSFP_C 0x1585
+
+RTE_PCI_DEV_ID_DECL_I40E(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_SFP_XL710)
+RTE_PCI_DEV_ID_DECL_I40E(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_SFP_X710)
+RTE_PCI_DEV_ID_DECL_I40E(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_QEMU)
+RTE_PCI_DEV_ID_DECL_I40E(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_KX_A)
+RTE_PCI_DEV_ID_DECL_I40E(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_KX_B)
+RTE_PCI_DEV_ID_DECL_I40E(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_KX_C)
+RTE_PCI_DEV_ID_DECL_I40E(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_KX_D)
+RTE_PCI_DEV_ID_DECL_I40E(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_QSFP_A)
+RTE_PCI_DEV_ID_DECL_I40E(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_QSFP_B)
+RTE_PCI_DEV_ID_DECL_I40E(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_QSFP_C)
+
/****************** Virtual IGB devices from e1000_hw.h ******************/
#define E1000_DEV_ID_82576_VF 0x10CA
@@ -468,6 +502,14 @@ RTE_PCI_DEV_ID_DECL_IXGBEVF(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82599_VF_HV)
RTE_PCI_DEV_ID_DECL_IXGBEVF(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_X540_VF)
RTE_PCI_DEV_ID_DECL_IXGBEVF(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_X540_VF_HV)
+/****************** Virtual I40E devices from i40e_type.h ********************/
+
+#define I40E_DEV_ID_VF 0x154C
+#define I40E_DEV_ID_VF_HV 0x1571
+
+RTE_PCI_DEV_ID_DECL_I40EVF(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_VF)
+RTE_PCI_DEV_ID_DECL_I40EVF(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_VF_HV)
+
/****************** Virtio devices from virtio.h ******************/
#define QUMRANET_DEV_ID_VIRTIO 0x1000
@@ -488,5 +530,7 @@ RTE_PCI_DEV_ID_DECL_VMXNET3(PCI_VENDOR_ID_VMWARE, VMWARE_DEV_ID_VMXNET3)
#undef RTE_PCI_DEV_ID_DECL_IGBVF
#undef RTE_PCI_DEV_ID_DECL_IXGBE
#undef RTE_PCI_DEV_ID_DECL_IXGBEVF
+#undef RTE_PCI_DEV_ID_DECL_I40E
+#undef RTE_PCI_DEV_ID_DECL_I40EVF
#undef RTE_PCI_DEV_ID_DECL_VIRTIO
#undef RTE_PCI_DEV_ID_DECL_VMXNET3
diff --git a/lib/librte_eal/linuxapp/igb_uio/igb_uio.c b/lib/librte_eal/linuxapp/igb_uio/igb_uio.c
index 09c40bf..79fe97d 100644
--- a/lib/librte_eal/linuxapp/igb_uio/igb_uio.c
+++ b/lib/librte_eal/linuxapp/igb_uio/igb_uio.c
@@ -79,6 +79,8 @@ static struct pci_device_id igbuio_pci_ids[] = {
#define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {PCI_DEVICE(vend, dev)},
#define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {PCI_DEVICE(vend, dev)},
#define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {PCI_DEVICE(vend, dev)},
+#define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {PCI_DEVICE(vend, dev)},
+#define RTE_PCI_DEV_ID_DECL_I40EVF(vend, dev) {PCI_DEVICE(vend, dev)},
#ifdef RTE_LIBRTE_VIRTIO_PMD
#define RTE_PCI_DEV_ID_DECL_VIRTIO(vend, dev) {PCI_DEVICE(vend, dev)},
#endif
diff --git a/lib/librte_ether/rte_ethdev.c b/lib/librte_ether/rte_ethdev.c
index a5727dd..1e2a16e 100644
--- a/lib/librte_ether/rte_ethdev.c
+++ b/lib/librte_ether/rte_ethdev.c
@@ -1194,6 +1194,21 @@ rte_eth_dev_get_vlan_offload(uint8_t port_id)
return ret;
}
+int
+rte_eth_dev_set_vlan_pvid(uint8_t port_id, uint16_t pvid, int on)
+{
+ struct rte_eth_dev *dev;
+
+ if (port_id >= nb_ports) {
+ PMD_DEBUG_TRACE("Invalid port_id=%d\n", port_id);
+ return (-ENODEV);
+ }
+ dev = &rte_eth_devices[port_id];
+ FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_pvid_set, -ENOTSUP);
+ (*dev->dev_ops->vlan_pvid_set)(dev, pvid, on);
+
+ return 0;
+}
int
rte_eth_dev_fdir_add_signature_filter(uint8_t port_id,
diff --git a/lib/librte_ether/rte_ethdev.h b/lib/librte_ether/rte_ethdev.h
index d5ea46b..899e5ff 100644
--- a/lib/librte_ether/rte_ethdev.h
+++ b/lib/librte_ether/rte_ethdev.h
@@ -230,6 +230,9 @@ struct rte_eth_link {
#define ETH_LINK_SPEED_100 100 /**< 100 megabits/second. */
#define ETH_LINK_SPEED_1000 1000 /**< 1 gigabits/second. */
#define ETH_LINK_SPEED_10000 10000 /**< 10 gigabits/second. */
+#define ETH_LINK_SPEED_10G 10000 /**< alias of 10 gigabits/second. */
+#define ETH_LINK_SPEED_20G 20000 /**< 20 gigabits/second. */
+#define ETH_LINK_SPEED_40G 40000 /**< 40 gigabits/second. */
#define ETH_LINK_AUTONEG_DUPLEX 0 /**< Auto-negotiate duplex. */
#define ETH_LINK_HALF_DUPLEX 1 /**< Half-duplex connection. */
@@ -308,29 +311,110 @@ struct rte_eth_rxmode {
* A structure used to configure the Receive Side Scaling (RSS) feature
* of an Ethernet port.
* If not NULL, the *rss_key* pointer of the *rss_conf* structure points
- * to an array of 40 bytes holding the RSS key to use for hashing specific
- * header fields of received packets.
- * Otherwise, a default random hash key is used by the device driver.
+ * to an array holding the RSS key to use for hashing specific header
+ * fields of received packets. The length of this array should be indicated
+ * by *rss_key_len* below. Otherwise, a default random hash key is used by
+ * the device driver.
+ *
+ * The *rss_key_len* field of the *rss_conf* structure indicates the length
+ * in bytes of the array pointed by *rss_key*. To be compitable, this length
+ * will be checked in i40e only. Others assume 40 bytes to be used as before.
*
* The *rss_hf* field of the *rss_conf* structure indicates the different
* types of IPv4/IPv6 packets to which the RSS hashing must be applied.
* Supplying an *rss_hf* equal to zero disables the RSS feature.
*/
struct rte_eth_rss_conf {
- uint8_t *rss_key; /**< If not NULL, 40-byte hash key. */
- uint16_t rss_hf; /**< Hash functions to apply - see below. */
+ uint8_t *rss_key; /**< If not NULL, 40-byte hash key. */
+ uint8_t rss_key_len; /**< hash key length in bytes. */
+ uint64_t rss_hf; /**< Hash functions to apply - see below. */
};
-#define ETH_RSS_IPV4 0x0001 /**< IPv4 packet. */
-#define ETH_RSS_IPV4_TCP 0x0002 /**< IPv4/TCP packet. */
-#define ETH_RSS_IPV6 0x0004 /**< IPv6 packet. */
-#define ETH_RSS_IPV6_EX 0x0008 /**< IPv6 packet with extension headers.*/
-#define ETH_RSS_IPV6_TCP 0x0010 /**< IPv6/TCP packet. */
-#define ETH_RSS_IPV6_TCP_EX 0x0020 /**< IPv6/TCP with extension headers. */
-/* Intel RSS extensions to UDP packets */
-#define ETH_RSS_IPV4_UDP 0x0040 /**< IPv4/UDP packet. */
-#define ETH_RSS_IPV6_UDP 0x0080 /**< IPv6/UDP packet. */
-#define ETH_RSS_IPV6_UDP_EX 0x0100 /**< IPv6/UDP with extension headers. */
+/* Supported RSS offloads */
+/* for 1G & 10G */
+#define ETH_RSS_IPV4_SHIFT 0
+#define ETH_RSS_IPV4_TCP_SHIFT 1
+#define ETH_RSS_IPV6_SHIFT 2
+#define ETH_RSS_IPV6_EX_SHIFT 3
+#define ETH_RSS_IPV6_TCP_SHIFT 4
+#define ETH_RSS_IPV6_TCP_EX_SHIFT 5
+#define ETH_RSS_IPV4_UDP_SHIFT 6
+#define ETH_RSS_IPV6_UDP_SHIFT 7
+#define ETH_RSS_IPV6_UDP_EX_SHIFT 8
+/* for 40G only */
+#define ETH_RSS_NONF_UNICAST_IPV4_UDP_SHIFT 29
+#define ETH_RSS_NONF_MULTICAST_IPV4_UDP_SHIFT 30
+#define ETH_RSS_NONF_IPV4_UDP_SHIFT 31
+#define ETH_RSS_NONF_IPV4_TCP_SYN_SHIFT 32
+#define ETH_RSS_NONF_IPV4_TCP_SHIFT 33
+#define ETH_RSS_NONF_IPV4_SCTP_SHIFT 34
+#define ETH_RSS_NONF_IPV4_OTHER_SHIFT 35
+#define ETH_RSS_FRAG_IPV4_SHIFT 36
+#define ETH_RSS_NONF_UNICAST_IPV6_UDP_SHIFT 39
+#define ETH_RSS_NONF_MULTICAST_IPV6_UDP_SHIFT 40
+#define ETH_RSS_NONF_IPV6_UDP_SHIFT 41
+#define ETH_RSS_NONF_IPV6_TCP_SYN_SHIFT 42
+#define ETH_RSS_NONF_IPV6_TCP_SHIFT 43
+#define ETH_RSS_NONF_IPV6_SCTP_SHIFT 44
+#define ETH_RSS_NONF_IPV6_OTHER_SHIFT 45
+#define ETH_RSS_FRAG_IPV6_SHIFT 46
+#define ETH_RSS_FCOE_OX_SHIFT 48
+#define ETH_RSS_FCOE_RX_SHIFT 49
+#define ETH_RSS_FCOE_OTHER_SHIFT 50
+#define ETH_RSS_L2_PAYLOAD_SHIFT 63
+
+/* for 1G & 10G */
+#define ETH_RSS_IPV4 ((uint16_t)1 << ETH_RSS_IPV4_SHIFT)
+#define ETH_RSS_IPV4_TCP ((uint16_t)1 << ETH_RSS_IPV4_TCP_SHIFT)
+#define ETH_RSS_IPV6 ((uint16_t)1 << ETH_RSS_IPV6_SHIFT)
+#define ETH_RSS_IPV6_EX ((uint16_t)1 << ETH_RSS_IPV6_EX_SHIFT)
+#define ETH_RSS_IPV6_TCP ((uint16_t)1 << ETH_RSS_IPV6_TCP_SHIFT)
+#define ETH_RSS_IPV6_TCP_EX ((uint16_t)1 << ETH_RSS_IPV6_TCP_EX_SHIFT)
+#define ETH_RSS_IPV4_UDP ((uint16_t)1 << ETH_RSS_IPV4_UDP_SHIFT)
+#define ETH_RSS_IPV6_UDP ((uint16_t)1 << ETH_RSS_IPV6_UDP_SHIFT)
+#define ETH_RSS_IPV6_UDP_EX ((uint16_t)1 << ETH_RSS_IPV6_UDP_EX_SHIFT)
+/* for 40G only */
+#define ETH_RSS_NONF_UNICAST_IPV4_UDP ((uint64_t)1 << ETH_RSS_NONF_UNICAST_IPV4_UDP_SHIFT)
+#define ETH_RSS_NONF_MULTICAST_IPV4_UDP ((uint64_t)1 << ETH_RSS_NONF_MULTICAST_IPV4_UDP_SHIFT)
+#define ETH_RSS_NONF_IPV4_UDP ((uint64_t)1 << ETH_RSS_NONF_IPV4_UDP_SHIFT)
+#define ETH_RSS_NONF_IPV4_TCP_SYN ((uint64_t)1 << ETH_RSS_NONF_IPV4_TCP_SYN_SHIFT)
+#define ETH_RSS_NONF_IPV4_TCP ((uint64_t)1 << ETH_RSS_NONF_IPV4_TCP_SHIFT)
+#define ETH_RSS_NONF_IPV4_SCTP ((uint64_t)1 << ETH_RSS_NONF_IPV4_SCTP_SHIFT)
+#define ETH_RSS_NONF_IPV4_OTHER ((uint64_t)1 << ETH_RSS_NONF_IPV4_OTHER_SHIFT)
+#define ETH_RSS_FRAG_IPV4 ((uint64_t)1 << ETH_RSS_FRAG_IPV4_SHIFT)
+#define ETH_RSS_NONF_UNICAST_IPV6_UDP ((uint64_t)1 << ETH_RSS_NONF_UNICAST_IPV6_UDP_SHIFT)
+#define ETH_RSS_NONF_MULTICAST_IPV6_UDP ((uint64_t)1 << ETH_RSS_NONF_MULTICAST_IPV6_UDP_SHIFT)
+#define ETH_RSS_NONF_IPV6_UDP ((uint64_t)1 << ETH_RSS_NONF_IPV6_UDP_SHIFT)
+#define ETH_RSS_NONF_IPV6_TCP_SYN ((uint64_t)1 << ETH_RSS_NONF_IPV6_TCP_SYN_SHIFT)
+#define ETH_RSS_NONF_IPV6_TCP ((uint64_t)1 << ETH_RSS_NONF_IPV6_TCP_SHIFT)
+#define ETH_RSS_NONF_IPV6_SCTP ((uint64_t)1 << ETH_RSS_NONF_IPV6_SCTP_SHIFT)
+#define ETH_RSS_NONF_IPV6_OTHER ((uint64_t)1 << ETH_RSS_NONF_IPV6_OTHER_SHIFT)
+#define ETH_RSS_FRAG_IPV6 ((uint64_t)1 << ETH_RSS_FRAG_IPV6_SHIFT)
+#define ETH_RSS_FCOE_OX ((uint64_t)1 << ETH_RSS_FCOE_OX_SHIFT)
+#define ETH_RSS_FCOE_RX ((uint64_t)1 << ETH_RSS_FCOE_RX_SHIFT)
+#define ETH_RSS_FCOE_OTHER ((uint64_t)1 << ETH_RSS_FCOE_OTHER_SHIFT)
+#define ETH_RSS_L2_PAYLOAD ((uint64_t)1 << ETH_RSS_L2_PAYLOAD_SHIFT)
+
+#define ETH_RSS_IP ( \
+ ETH_RSS_IPV4 | \
+ ETH_RSS_IPV6 | \
+ ETH_RSS_NONF_IPV4_OTHER | \
+ ETH_RSS_FRAG_IPV4 | \
+ ETH_RSS_NONF_IPV6_OTHER | \
+ ETH_RSS_FRAG_IPV6)
+#define ETH_RSS_UDP ( \
+ ETH_RSS_IPV4 | \
+ ETH_RSS_IPV6 | \
+ ETH_RSS_IPV4_UDP | \
+ ETH_RSS_IPV6_UDP | \
+ ETH_RSS_IPV6_UDP_EX | \
+ ETH_RSS_NONF_UNICAST_IPV4_UDP | \
+ ETH_RSS_NONF_MULTICAST_IPV4_UDP | \
+ ETH_RSS_NONF_IPV4_UDP | \
+ ETH_RSS_NONF_UNICAST_IPV6_UDP | \
+ ETH_RSS_NONF_MULTICAST_IPV6_UDP | \
+ ETH_RSS_NONF_IPV6_UDP)
+
/* Definitions used for redirection table entry size */
#define ETH_RSS_RETA_NUM_ENTRIES 128
#define ETH_RSS_RETA_MAX_QUEUE 16
@@ -359,7 +443,6 @@ struct rte_eth_rss_conf {
/* Definitions used for receive MAC address */
#define ETH_NUM_RECEIVE_MAC_ADDR 128 /**< Maximum nb. of receive mac addr. */
-
/* Definitions used for unicast hash */
#define ETH_VMDQ_NUM_UC_HASH_ARRAY 128 /**< Maximum nb. of UC hash array. */
@@ -492,6 +575,15 @@ struct rte_eth_vmdq_rx_conf {
*/
struct rte_eth_txmode {
enum rte_eth_tx_mq_mode mq_mode; /**< TX multi-queues mode. */
+
+ /* For i40e specifically */
+ uint16_t pvid;
+ uint8_t hw_vlan_reject_tagged : 1,
+ /**< If set, reject sending out tagged pkts */
+ hw_vlan_reject_untagged : 1,
+ /**< If set, reject sending out untagged pkts */
+ hw_vlan_insert_pvid : 1;
+ /**< If set, enable port based VLAN insertion */
};
/**
@@ -896,6 +988,11 @@ typedef void (*vlan_tpid_set_t)(struct rte_eth_dev *dev,
typedef void (*vlan_offload_set_t)(struct rte_eth_dev *dev, int mask);
/**< @internal set VLAN offload function by an Ethernet device. */
+typedef int (*vlan_pvid_set_t)(struct rte_eth_dev *dev,
+ uint16_t vlan_id,
+ int on);
+/**< @internal set port based TX VLAN insertion by an Ethernet device. */
+
typedef void (*vlan_strip_queue_set_t)(struct rte_eth_dev *dev,
uint16_t rx_queue_id,
int on);
@@ -1099,6 +1196,7 @@ struct eth_dev_ops {
vlan_tpid_set_t vlan_tpid_set; /**< Outer VLAN TPID Setup. */
vlan_strip_queue_set_t vlan_strip_queue_set; /**< VLAN Stripping on queue. */
vlan_offload_set_t vlan_offload_set; /**< Set VLAN Offload. */
+ vlan_pvid_set_t vlan_pvid_set; /**< Set port based TX VLAN insertion */
eth_rx_queue_setup_t rx_queue_setup;/**< Set up device RX queue.*/
eth_queue_release_t rx_queue_release;/**< Release RX queue.*/
eth_rx_queue_count_t rx_queue_count; /**< Get Rx queue count. */
@@ -1751,6 +1849,22 @@ extern int rte_eth_dev_set_vlan_offload(uint8_t port_id, int offload_mask);
extern int rte_eth_dev_get_vlan_offload(uint8_t port_id);
/**
+ * Set port based TX VLAN insersion on or off.
+ *
+ * @param port_id
+ * The port identifier of the Ethernet device.
+ * @param pvid
+ * Port based TX VLAN identifier togeth with user priority.
+ * @param on
+ * Turn on or off the port based TX VLAN insertion.
+ *
+ * @return
+ * - (0) if successful.
+ * - negative if failed.
+ */
+extern int rte_eth_dev_set_vlan_pvid(uint8_t port_id, uint16_t pvid, int on);
+
+/**
*
* Retrieve a burst of input packets from a receive queue of an Ethernet
* device. The retrieved packets are stored in *rte_mbuf* structures whose
diff --git a/lib/librte_ether/rte_ether.h b/lib/librte_ether/rte_ether.h
index 71dc788..1799980 100644
--- a/lib/librte_ether/rte_ether.h
+++ b/lib/librte_ether/rte_ether.h
@@ -86,6 +86,30 @@ struct ether_addr {
#define ETHER_GROUP_ADDR 0x01 /**< Multicast or broadcast Eth. address. */
/**
+ * Check if two Ethernet addresses are the same.
+ *
+ * @param ea1
+ * A pointer to the first ether_addr structure containing
+ * the ethernet address.
+ * @param ea2
+ * A pointer to the second ether_addr structure containing
+ * the ethernet address.
+ *
+ * @return
+ * True (1) if the given two ethernet address are the same;
+ * False (0) otherwise.
+ */
+static inline int is_same_ether_addr(const struct ether_addr *ea1,
+ const struct ether_addr *ea2)
+{
+ int i;
+ for (i = 0; i < ETHER_ADDR_LEN; i++)
+ if (ea1->addr_bytes[i] != ea2->addr_bytes[i])
+ return 0;
+ return 1;
+}
+
+/**
* Check if an Ethernet address is filled with zeros.
*
* @param ea
diff --git a/lib/librte_mbuf/rte_mbuf.h b/lib/librte_mbuf/rte_mbuf.h
index 4a9ab41..ded2ce6 100644
--- a/lib/librte_mbuf/rte_mbuf.h
+++ b/lib/librte_mbuf/rte_mbuf.h
@@ -85,6 +85,11 @@ struct rte_ctrlmbuf {
#define PKT_RX_FDIR 0x0004 /**< RX packet with FDIR infos. */
#define PKT_RX_L4_CKSUM_BAD 0x0008 /**< L4 cksum of RX pkt. is not OK. */
#define PKT_RX_IP_CKSUM_BAD 0x0010 /**< IP cksum of RX pkt. is not OK. */
+#define PKT_RX_EIP_CKSUM_BAD 0x0000 /**< External IP header checksum error. */
+#define PKT_RX_OVERSIZE 0x0000 /**< Num of desc of an RX pkt oversize. */
+#define PKT_RX_HBUF_OVERFLOW 0x0000 /**< Header buffer overflow. */
+#define PKT_RX_RECIP_ERR 0x0000 /**< Hardware processing error. */
+#define PKT_RX_MAC_ERR 0x0000 /**< MAC error. */
#define PKT_RX_IPV4_HDR 0x0020 /**< RX packet with IPv4 header. */
#define PKT_RX_IPV4_HDR_EXT 0x0040 /**< RX packet with extended IPv4 header. */
#define PKT_RX_IPV6_HDR 0x0080 /**< RX packet with IPv6 header. */
@@ -94,6 +99,9 @@ struct rte_ctrlmbuf {
#define PKT_TX_VLAN_PKT 0x0800 /**< TX packet is a 802.1q VLAN packet. */
#define PKT_TX_IP_CKSUM 0x1000 /**< IP cksum of TX pkt. computed by NIC. */
+#define PKT_TX_IPV4_CSUM 0x1000 /**< Alias of PKT_TX_IP_CKSUM. */
+#define PKT_TX_IPV4 PKT_RX_IPV4_HDR /**< IPv4 with no IP checksum offload. */
+#define PKT_TX_IPV6 PKT_RX_IPV6_HDR /**< IPv6 packet */
/*
* Bit 14~13 used for L4 packet type with checksum enabled.
* 00: Reserved
diff --git a/mk/rte.app.mk b/mk/rte.app.mk
index 38c68b8..f0a659d 100644
--- a/mk/rte.app.mk
+++ b/mk/rte.app.mk
@@ -161,6 +161,10 @@ ifeq ($(CONFIG_RTE_LIBRTE_VIRTIO_PMD),y)
LDLIBS += -lrte_pmd_virtio_uio
endif
+ifeq ($(CONFIG_RTE_LIBRTE_I40E_PMD),y)
+LDLIBS += -lrte_pmd_i40e
+endif
+
ifeq ($(CONFIG_RTE_LIBRTE_IXGBE_PMD),y)
LDLIBS += -lrte_pmd_ixgbe
endif
--
1.8.1.4
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