[dpdk-dev] [PATCH 21/22] config: add configurations for enabling 'Extended Tag' or resetting 'Max Read Request Size'

Helin Zhang helin.zhang at intel.com
Wed May 21 17:30:20 CEST 2014


Sys files of 'extended_tag' and 'max_read_request_size' have been
supported in igb_uio, and can be changed during probing PCI. Three
items in configuration files are needed to support them at compile
time. Those three items are,
 - CONFIG_RTE_PCI_CONFIG
 - CONFIG_RTE_PCI_EXTENDED_TAG
 - CONFIG_RTE_PCI_MAX_READ_REQUEST_SIZE

Signed-off-by: Helin Zhang <helin.zhang at intel.com>
Signed-off-by: Mark Chen <jing.d.chen at intel.com>
---
 config/defconfig_i686-default-linuxapp-gcc   | 10 ++++++++++
 config/defconfig_i686-default-linuxapp-icc   | 10 ++++++++++
 config/defconfig_x86_64-default-linuxapp-gcc | 10 ++++++++++
 config/defconfig_x86_64-default-linuxapp-icc | 10 ++++++++++
 4 files changed, 40 insertions(+)

diff --git a/config/defconfig_i686-default-linuxapp-gcc b/config/defconfig_i686-default-linuxapp-gcc
index 931f6c5..21264d9 100644
--- a/config/defconfig_i686-default-linuxapp-gcc
+++ b/config/defconfig_i686-default-linuxapp-gcc
@@ -125,6 +125,16 @@ CONFIG_RTE_EAL_ALLOW_INV_SOCKET_ID=n
 CONFIG_RTE_EAL_ALWAYS_PANIC_ON_ERROR=n
 
 #
+# Special configurations in PCI Config Space for high performance
+# CONFIG_RTE_PCI_CONFIG is the compile switch for two features below
+# CONFIG_RTE_PCI_EXTENDED_TAG can be "on", "off"
+# CONFIG_RTE_PCI_MAX_READ_REQUEST_SIZE can be 128, 256, 512, 1024, 2048, 4096
+#
+CONFIG_RTE_PCI_CONFIG=n
+CONFIG_RTE_PCI_EXTENDED_TAG=""
+CONFIG_RTE_PCI_MAX_READ_REQUEST_SIZE=0
+
+#
 # Compile Environment Abstraction Layer for linux
 #
 CONFIG_RTE_LIBRTE_EAL_LINUXAPP=y
diff --git a/config/defconfig_i686-default-linuxapp-icc b/config/defconfig_i686-default-linuxapp-icc
index b07bd76..b32dfdf 100644
--- a/config/defconfig_i686-default-linuxapp-icc
+++ b/config/defconfig_i686-default-linuxapp-icc
@@ -125,6 +125,16 @@ CONFIG_RTE_EAL_ALLOW_INV_SOCKET_ID=n
 CONFIG_RTE_EAL_ALWAYS_PANIC_ON_ERROR=n
 
 #
+# Special configurations in PCI Config Space for high performance
+# CONFIG_RTE_PCI_CONFIG is the compile switch for two features below
+# CONFIG_RTE_PCI_EXTENDED_TAG can be "on", "off"
+# CONFIG_RTE_PCI_MAX_READ_REQUEST_SIZE can be 128, 256, 512, 1024, 2048, 4096
+#
+CONFIG_RTE_PCI_CONFIG=n
+CONFIG_RTE_PCI_EXTENDED_TAG=""
+CONFIG_RTE_PCI_MAX_READ_REQUEST_SIZE=0
+
+#
 # Compile Environment Abstraction Layer for linux
 #
 CONFIG_RTE_LIBRTE_EAL_LINUXAPP=y
diff --git a/config/defconfig_x86_64-default-linuxapp-gcc b/config/defconfig_x86_64-default-linuxapp-gcc
index b8ccb2f..c398906 100644
--- a/config/defconfig_x86_64-default-linuxapp-gcc
+++ b/config/defconfig_x86_64-default-linuxapp-gcc
@@ -125,6 +125,16 @@ CONFIG_RTE_EAL_ALLOW_INV_SOCKET_ID=n
 CONFIG_RTE_EAL_ALWAYS_PANIC_ON_ERROR=n
 
 #
+# Special configurations in PCI Config Space for high performance
+# CONFIG_RTE_PCI_CONFIG is the compile switch for two features below
+# CONFIG_RTE_PCI_EXTENDED_TAG can be "on", "off"
+# CONFIG_RTE_PCI_MAX_READ_REQUEST_SIZE can be 128, 256, 512, 1024, 2048, 4096
+#
+CONFIG_RTE_PCI_CONFIG=n
+CONFIG_RTE_PCI_EXTENDED_TAG=""
+CONFIG_RTE_PCI_MAX_READ_REQUEST_SIZE=0
+
+#
 # Compile Environment Abstraction Layer for linux
 #
 CONFIG_RTE_LIBRTE_EAL_LINUXAPP=y
diff --git a/config/defconfig_x86_64-default-linuxapp-icc b/config/defconfig_x86_64-default-linuxapp-icc
index 58a6c62..5732cd0 100644
--- a/config/defconfig_x86_64-default-linuxapp-icc
+++ b/config/defconfig_x86_64-default-linuxapp-icc
@@ -125,6 +125,16 @@ CONFIG_RTE_EAL_ALLOW_INV_SOCKET_ID=n
 CONFIG_RTE_EAL_ALWAYS_PANIC_ON_ERROR=n
 
 #
+# Special configurations in PCI Config Space for high performance
+# CONFIG_RTE_PCI_CONFIG is the compile switch for two features below
+# CONFIG_RTE_PCI_EXTENDED_TAG can be "on", "off"
+# CONFIG_RTE_PCI_MAX_READ_REQUEST_SIZE can be 128, 256, 512, 1024, 2048, 4096
+#
+CONFIG_RTE_PCI_CONFIG=n
+CONFIG_RTE_PCI_EXTENDED_TAG=""
+CONFIG_RTE_PCI_MAX_READ_REQUEST_SIZE=0
+
+#
 # Compile Environment Abstraction Layer for linux
 #
 CONFIG_RTE_LIBRTE_EAL_LINUXAPP=y
-- 
1.8.1.4



More information about the dev mailing list