[dpdk-dev] [PATCH 3/5] bnx2x: Add RTE_LIBRTE_BNX2X_REG_ACCESS config option

[Rasesh Mody]

From: Harish Patil <harish.patil at qlogic.com>

Signed-off-by: Harish Patil <harish.patil at qlogic.com>
---
 config/common_linuxapp         |    1 +
 drivers/net/bnx2x/Makefile     |    2 +-
 drivers/net/bnx2x/bnx2x.h      |    2 +-
 drivers/net/bnx2x/bnx2x_logs.h |    8 ++++++++
 drivers/net/bnx2x/debug.c      |   24 ++++++++++++++----------
 5 files changed, 25 insertions(+), 12 deletions(-)

diff --git a/config/common_linuxapp b/config/common_linuxapp
index 0de43d5..013fa0d 100644
--- a/config/common_linuxapp
+++ b/config/common_linuxapp
@@ -220,6 +220,7 @@ CONFIG_RTE_LIBRTE_BNX2X_DEBUG_INIT=n
 CONFIG_RTE_LIBRTE_BNX2X_DEBUG_RX=n
 CONFIG_RTE_LIBRTE_BNX2X_DEBUG_TX=n
 CONFIG_RTE_LIBRTE_BNX2X_MF_SUPPORT=n
+CONFIG_RTE_LIBRTE_BNX2X_REG_ACCESS=n
 
 #
 # Compile burst-oriented Chelsio Terminator 10GbE/40GbE (CXGBE) PMD
diff --git a/drivers/net/bnx2x/Makefile b/drivers/net/bnx2x/Makefile
index 87f31b6..6b2df22 100644
--- a/drivers/net/bnx2x/Makefile
+++ b/drivers/net/bnx2x/Makefile
@@ -23,7 +23,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_BNX2X_PMD) += bnx2x_ethdev.c
 SRCS-$(CONFIG_RTE_LIBRTE_BNX2X_PMD) += ecore_sp.c
 SRCS-$(CONFIG_RTE_LIBRTE_BNX2X_PMD) += elink.c
 SRCS-$(CONFIG_RTE_LIBRTE_BNX2X_PMD) += bnx2x_vfpf.c
-SRCS-$(CONFIG_RTE_LIBRTE_BNX2X_DEBUG) += debug.c
+SRCS-$(CONFIG_RTE_LIBRTE_BNX2X_REG_ACCESS) += debug.c
 
 # this lib depends upon:
 DEPDIRS-$(CONFIG_RTE_LIBRTE_BNX2X_PMD) += lib/librte_eal lib/librte_ether lib/librte_hash
diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h
index 867b92a..ffd101c 100644
--- a/drivers/net/bnx2x/bnx2x.h
+++ b/drivers/net/bnx2x/bnx2x.h
@@ -1445,7 +1445,7 @@ struct bnx2x_func_init_params {
 #define BAR1 2
 #define BAR2 4
 
-#ifdef RTE_LIBRTE_BNX2X_DEBUG
+#ifdef RTE_LIBRTE_BNX2X_REG_ACCESS
 uint8_t bnx2x_reg_read8(struct bnx2x_softc *sc, size_t offset);
 uint16_t bnx2x_reg_read16(struct bnx2x_softc *sc, size_t offset);
 uint32_t bnx2x_reg_read32(struct bnx2x_softc *sc, size_t offset);
diff --git a/drivers/net/bnx2x/bnx2x_logs.h b/drivers/net/bnx2x/bnx2x_logs.h
index d31c253..7ef6e64 100644
--- a/drivers/net/bnx2x/bnx2x_logs.h
+++ b/drivers/net/bnx2x/bnx2x_logs.h
@@ -47,4 +47,12 @@
 #define PMD_DRV_LOG(level, fmt, args...) \
 	PMD_DRV_LOG_RAW(level, fmt "\n", ## args)
 
+#ifdef RTE_LIBRTE_BNX2X_REG_ACCESS
+#define PMD_REG_ACCESS_LOG(level, fmt, args...) \
+	RTE_LOG(level, PMD, "%s(): " fmt "\n", __func__, ## args)
+#else
+#define PMD_REG_ACCESS_LOG(level, fmt, args...) do { } while(0)
+#endif
+
+
 #endif /* _PMD_LOGS_H_ */
diff --git a/drivers/net/bnx2x/debug.c b/drivers/net/bnx2x/debug.c
index 9ab4f1d..b5e29f7 100644
--- a/drivers/net/bnx2x/debug.c
+++ b/drivers/net/bnx2x/debug.c
@@ -44,7 +44,7 @@
 void
 bnx2x_reg_write8(struct bnx2x_softc *sc, size_t offset, uint8_t val)
 {
-	PMD_DRV_LOG(DEBUG, "offset=0x%08lx val=0x%02x", offset, val);
+	PMD_REG_ACCESS_LOG(DEBUG, "offset=0x%08lx val=0x%02x", offset, val);
 	*((volatile uint8_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)) = val;
 }
 
@@ -52,10 +52,11 @@ void
 bnx2x_reg_write16(struct bnx2x_softc *sc, size_t offset, uint16_t val)
 {
 	if ((offset % 2) != 0) {
-		PMD_DRV_LOG(DEBUG, "Unaligned 16-bit write to 0x%08lx", offset);
+		PMD_DRV_LOG(NOTICE, "Unaligned 16-bit write to 0x%08lx",
+			    offset);
 	}
 
-	PMD_DRV_LOG(DEBUG, "offset=0x%08lx val=0x%04x", offset, val);
+	PMD_REG_ACCESS_LOG(DEBUG, "offset=0x%08lx val=0x%04x", offset, val);
 	*((volatile uint16_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)) = val;
 }
 
@@ -63,10 +64,11 @@ void
 bnx2x_reg_write32(struct bnx2x_softc *sc, size_t offset, uint32_t val)
 {
 	if ((offset % 4) != 0) {
-		PMD_DRV_LOG(DEBUG, "Unaligned 32-bit write to 0x%08lx", offset);
+		PMD_DRV_LOG(NOTICE, "Unaligned 32-bit write to 0x%08lx",
+			    offset);
 	}
 
-	PMD_DRV_LOG(DEBUG, "offset=0x%08lx val=0x%08x", offset, val);
+	PMD_REG_ACCESS_LOG(DEBUG, "offset=0x%08lx val=0x%08x", offset, val);
 	*((volatile uint32_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)) = val;
 }
 
@@ -76,7 +78,7 @@ bnx2x_reg_read8(struct bnx2x_softc *sc, size_t offset)
 	uint8_t val;
 
 	val = (uint8_t)(*((volatile uint8_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)));
-	PMD_DRV_LOG(DEBUG, "offset=0x%08lx val=0x%02x", offset, val);
+	PMD_REG_ACCESS_LOG(DEBUG, "offset=0x%08lx val=0x%02x", offset, val);
 
 	return (val);
 }
@@ -87,11 +89,12 @@ bnx2x_reg_read16(struct bnx2x_softc *sc, size_t offset)
 	uint16_t val;
 
 	if ((offset % 2) != 0) {
-		PMD_DRV_LOG(DEBUG, "Unaligned 16-bit read from 0x%08lx", offset);
+		PMD_DRV_LOG(NOTICE, "Unaligned 16-bit read from 0x%08lx",
+			    offset);
 	}
 
 	val = (uint16_t)(*((volatile uint16_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)));
-	PMD_DRV_LOG(DEBUG, "offset=0x%08lx val=0x%08x", offset, val);
+	PMD_REG_ACCESS_LOG(DEBUG, "offset=0x%08lx val=0x%08x", offset, val);
 
 	return (val);
 }
@@ -102,12 +105,13 @@ bnx2x_reg_read32(struct bnx2x_softc *sc, size_t offset)
 	uint32_t val;
 
 	if ((offset % 4) != 0) {
-		PMD_DRV_LOG(DEBUG, "Unaligned 32-bit read from 0x%08lx", offset);
+		PMD_DRV_LOG(NOTICE, "Unaligned 32-bit read from 0x%08lx",
+			    offset);
 		return 0;
 	}
 
 	val = (uint32_t)(*((volatile uint32_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)));
-	PMD_DRV_LOG(DEBUG, "offset=0x%08lx val=0x%08x", offset, val);
+	PMD_REG_ACCESS_LOG(DEBUG, "offset=0x%08lx val=0x%08x", offset, val);
 
 	return (val);
 }
-- 
1.7.10.3