[dpdk-dev] [PATCH 27/29] net/ixgbe/base: add write flush required by Inphi

[Ferruh Yigit]

On 12/4/2016 6:31 AM, Wei Dai wrote:
> This patch updates Inphi configuration to flush the register write with

Do we really need to mention from Inphi here? If so, can you please
explain what it is?

> a reg read. Inphi is configured in ixgbe_setup_mac_link_sfp_x550a.
> The Inphy setup flow has been updated to read configuration reg, write
> only linear/non-linear, and then read (write flush).

Also patch does [1] seems not mentioned in the commit log, can you
please add information for it?

[1]
> +		reg_phy_ext &= ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) |
> +				 (IXGBE_CS4227_EDC_MODE_SR << 1));

> 
> Signed-off-by: Wei Dai <wei.dai at intel.com>
> ---
>  drivers/net/ixgbe/base/ixgbe_x550.c | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/drivers/net/ixgbe/base/ixgbe_x550.c b/drivers/net/ixgbe/base/ixgbe_x550.c
> index 4a98530..a57ba74 100644
> --- a/drivers/net/ixgbe/base/ixgbe_x550.c
> +++ b/drivers/net/ixgbe/base/ixgbe_x550.c
> @@ -2834,12 +2834,26 @@ s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
>  
>  		/* Configure CS4227/CS4223 LINE side to proper mode. */
>  		reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
> +
> +		ret_val = hw->phy.ops.read_reg(hw, reg_slice,
> +					IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
> +
> +		if (ret_val != IXGBE_SUCCESS)
> +			return ret_val;
> +
> +		reg_phy_ext &= ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) |
> +				 (IXGBE_CS4227_EDC_MODE_SR << 1));
> +
>  		if (setup_linear)
>  			reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
>  		else
>  			reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
>  		ret_val = hw->phy.ops.write_reg(hw, reg_slice,
>  					 IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
> +
> +		/* Flush previous write with a read */
> +		ret_val = hw->phy.ops.read_reg(hw, reg_slice,
> +					IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
>  	}
>  	return ret_val;
>  }
>