[dpdk-dev] [PATCH 14/28] crypto/qat: use eal I/O device memory read/write API

Jerin Jacob jerin.jacob at caviumnetworks.com
Wed Dec 14 02:55:44 CET 2016


From: Santosh Shukla <santosh.shukla at caviumnetworks.com>

Replace the raw I/O device memory read/write access with eal
abstraction for I/O device memory read/write access to fix portability
issues across different architectures.

Signed-off-by: Santosh Shukla <santosh.shukla at caviumnetworks.com>
Signed-off-by: Jerin Jacob <jerin.jacob at caviumnetworks.com>
CC: John Griffin <john.griffin at intel.com>
CC: Fiona Trahe <fiona.trahe at intel.com>
CC: Deepak Kumar Jain <deepak.k.jain at intel.com>
---
 drivers/crypto/qat/qat_adf/adf_transport_access_macros.h | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/drivers/crypto/qat/qat_adf/adf_transport_access_macros.h b/drivers/crypto/qat/qat_adf/adf_transport_access_macros.h
index 47f1c91..a6e407d 100644
--- a/drivers/crypto/qat/qat_adf/adf_transport_access_macros.h
+++ b/drivers/crypto/qat/qat_adf/adf_transport_access_macros.h
@@ -47,14 +47,19 @@
 #ifndef ADF_TRANSPORT_ACCESS_MACROS_H
 #define ADF_TRANSPORT_ACCESS_MACROS_H
 
+#include <rte_io.h>
+
 /* CSR write macro */
-#define ADF_CSR_WR(csrAddr, csrOffset, val) \
-	(void)((*((volatile uint32_t *)(((uint8_t *)csrAddr) + csrOffset)) \
-			= (val)))
+#define ADF_CSR_WR(csrAddr, csrOffset, val) ({			\
+	rte_writel(val, (((uint8_t *)csrAddr) + csrOffset));	\
+})
 
 /* CSR read macro */
-#define ADF_CSR_RD(csrAddr, csrOffset) \
-	(*((volatile uint32_t *)(((uint8_t *)csrAddr) + csrOffset)))
+#define ADF_CSR_RD(csrAddr, csrOffset) ({			\
+	uint32_t __val;						\
+	__val = rte_readl(((uint8_t *)csrAddr) + csrOffset);	\
+	__val;							\
+})
 
 #define ADF_BANK_INT_SRC_SEL_MASK_0 0x4444444CUL
 #define ADF_BANK_INT_SRC_SEL_MASK_X 0x44444444UL
-- 
2.5.5



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