[dpdk-dev] [PATCH v2 1/2] drivers/i40e: fix X722 macro absence result in compile
Ananyev, Konstantin
konstantin.ananyev at intel.com
Sun Oct 16 15:31:17 CEST 2016
Hi Jeff,
> -----Original Message-----
> From: dev [mailto:dev-bounces at dpdk.org] On Behalf Of Jeff Guo
> Sent: Sunday, October 16, 2016 2:40 AM
> To: Zhang, Helin <helin.zhang at intel.com>; Wu, Jingjing <jingjing.wu at intel.com>
> Cc: dev at dpdk.org; Guo, Jia <jia.guo at intel.com>
> Subject: [dpdk-dev] [PATCH v2 1/2] drivers/i40e: fix X722 macro absence result in compile
>
> Since some register only be supported by X722 but may not be supported
> by other NICs, so add X722 macro to distinguish that to avoid compile error
> when the X722 macro is undefined.
Two probably silly questions:
1) So who will setup X722_SUPPORT macro?
Is that a user responsibility when he is building dpdk i40e PMD?
If so, why it is not a rte_config option?
2) Why this all has to be build time decision?
Why nor run-time?
Why i40e driver can't support all devices (including x722)
and invoke different config functions (write different registers)
based on device type/id information?
As it does for other device types/ids?
Konstantin
>
> Fixes: d0a349409bd7 (“i40e: support AQ based RSS config”)
> Fixes: 001a1c0f98f4 ("ethdev: get registers width")
> Fixes: a0454b5d2e08 (“i40e: update device ids”)
> Fixes: 647d1eaf758b (“i40evf: support AQ based RSS config”)
> Fixes: 3058891a2b02 (“net/i40e: move PCI device ids to the driver”)
> Fixes: d9efd0136ac1 (“i40e: add EEPROM and registers dumping”)
> Signed-off-by: Jeff Guo <jia.guo at intel.com>
>
> ---
> v2:
> fix compile error when x722 macro is not define.
> ---
> drivers/net/i40e/i40e_ethdev.c | 36 ++++++++++++++-
> drivers/net/i40e/i40e_ethdev.h | 17 +++++++
> drivers/net/i40e/i40e_ethdev_vf.c | 27 +++++++++++
> drivers/net/i40e/i40e_regs.h | 96 +++++++++++++++++++++++++++++++++++++++
> drivers/net/i40e/i40e_rxtx.c | 18 +++++++-
> 5 files changed, 191 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
> index d0640b9..920fd6d 100644
> --- a/drivers/net/i40e/i40e_ethdev.c
> +++ b/drivers/net/i40e/i40e_ethdev.c
> @@ -468,13 +468,17 @@ static const struct rte_pci_id pci_id_i40e_map[] = {
> { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
> { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
> { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
> +#ifdef X722_SUPPORT
> +#ifdef X722_A0_SUPPORT
> { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
> +#endif /* X722_A0_SUPPORT */
> { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
> { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
> { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
> { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
> { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
> { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
> +#endif /* X722_SUPPORT */
> { .vendor_id = 0, /* sentinel */ },
> };
>
> @@ -3182,6 +3186,7 @@ i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
> if (!lut)
> return -EINVAL;
>
> +#ifdef X722_SUPPORT
> if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
> ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
> lut, lut_size);
> @@ -3190,12 +3195,15 @@ i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
> return ret;
> }
> } else {
> +#endif /* X722_SUPPORT */
> uint32_t *lut_dw = (uint32_t *)lut;
> uint16_t i, lut_size_dw = lut_size / 4;
>
> for (i = 0; i < lut_size_dw; i++)
> lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
> +#ifdef X722_SUPPORT
> }
> +#endif /* X722_SUPPORT */
>
> return 0;
> }
> @@ -3213,6 +3221,7 @@ i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
> pf = I40E_VSI_TO_PF(vsi);
> hw = I40E_VSI_TO_HW(vsi);
>
> +#ifdef X722_SUPPORT
> if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
> ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
> lut, lut_size);
> @@ -3221,13 +3230,16 @@ i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
> return ret;
> }
> } else {
> +#endif /* X722_SUPPORT */
> uint32_t *lut_dw = (uint32_t *)lut;
> uint16_t i, lut_size_dw = lut_size / 4;
>
> for (i = 0; i < lut_size_dw; i++)
> I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
> I40E_WRITE_FLUSH(hw);
> +#ifdef X722_SUPPORT
> }
> +#endif /* X722_SUPPORT */
>
> return 0;
> }
> @@ -3508,8 +3520,10 @@ i40e_pf_parameter_init(struct rte_eth_dev *dev)
> pf->lan_nb_qps = 1;
> } else {
> pf->flags |= I40E_FLAG_RSS;
> +#ifdef X722_SUPPORT
> if (hw->mac.type == I40E_MAC_X722)
> pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
> +#endif /* X722_SUPPORT */
> pf->lan_nb_qps = pf->lan_nb_qp_max;
> }
> qp_count += pf->lan_nb_qps;
> @@ -6302,6 +6316,7 @@ i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
> return -EINVAL;
> }
>
> +#ifdef X722_SUPPORT
> if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
> struct i40e_aqc_get_set_rss_key_data *key_dw =
> (struct i40e_aqc_get_set_rss_key_data *)key;
> @@ -6311,13 +6326,16 @@ i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
> PMD_INIT_LOG(ERR, "Failed to configure RSS key "
> "via AQ");
> } else {
> +#endif /* X722_SUPPORT */
> uint32_t *hash_key = (uint32_t *)key;
> uint16_t i;
>
> for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
> i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
> I40E_WRITE_FLUSH(hw);
> +#ifdef X722_SUPPORT
> }
> +#endif /* X722_SUPPORT */
>
> return ret;
> }
> @@ -6332,6 +6350,7 @@ i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
> if (!key || !key_len)
> return -EINVAL;
>
> +#ifdef X722_SUPPORT
> if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
> ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
> (struct i40e_aqc_get_set_rss_key_data *)key);
> @@ -6340,12 +6359,16 @@ i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
> return ret;
> }
> } else {
> +#endif /* X722_SUPPORT */
> uint32_t *key_dw = (uint32_t *)key;
> uint16_t i;
>
> for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
> key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
> +#ifdef X722_SUPPORT
> }
> +#endif /* X722_SUPPORT */
> +
> *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
>
> return 0;
> @@ -9610,8 +9633,17 @@ static int i40e_get_regs(struct rte_eth_dev *dev,
> const struct i40e_reg_info *reg_info;
>
> if (ptr_data == NULL) {
> - regs->length = I40E_GLGEN_STAT_CLEAR + 4;
> - regs->width = sizeof(uint32_t);
> +#ifdef X722_SUPPORT
> + if (hw->mac.type == I40E_MAC_X722) {
> + regs->length = I40E_GLGEN_STAT_CLEAR + 4;
> +#else
> + regs->length = I40E_GLVEBVL_BPCH(
> + I40E_GLVEBVL_BPCH_MAX_INDEX) + 0x8;
> +#endif /* X722_SUPPORT */
> + regs->width = sizeof(uint32_t);
> +#ifdef X722_SUPPORT
> + }
> +#endif /* X722_SUPPORT */
> return 0;
> }
>
> diff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h
> index 57a8ae1..43711b8 100644
> --- a/drivers/net/i40e/i40e_ethdev.h
> +++ b/drivers/net/i40e/i40e_ethdev.h
> @@ -125,7 +125,10 @@ enum i40e_flxpld_layer_idx {
> #define I40E_FLAG_HEADER_SPLIT_ENABLED (1ULL << 5)
> #define I40E_FLAG_FDIR (1ULL << 6)
> #define I40E_FLAG_VXLAN (1ULL << 7)
> +#ifdef X722_SUPPORT
> #define I40E_FLAG_RSS_AQ_CAPABLE (1ULL << 8)
> +#endif /* X722_SUPPORT */
> +#ifdef X722_SUPPORT
> #define I40E_FLAG_ALL (I40E_FLAG_RSS | \
> I40E_FLAG_DCB | \
> I40E_FLAG_VMDQ | \
> @@ -135,6 +138,16 @@ enum i40e_flxpld_layer_idx {
> I40E_FLAG_FDIR | \
> I40E_FLAG_VXLAN | \
> I40E_FLAG_RSS_AQ_CAPABLE)
> +#else
> +#define I40E_FLAG_ALL (I40E_FLAG_RSS | \
> + I40E_FLAG_DCB | \
> + I40E_FLAG_VMDQ | \
> + I40E_FLAG_SRIOV | \
> + I40E_FLAG_HEADER_SPLIT_DISABLED | \
> + I40E_FLAG_HEADER_SPLIT_ENABLED | \
> + I40E_FLAG_FDIR | \
> + I40E_FLAG_VXLAN)
> +#endif /* X722_SUPPORT */
>
> #define I40E_RSS_OFFLOAD_ALL ( \
> ETH_RSS_FRAG_IPV4 | \
> @@ -650,7 +663,11 @@ i40e_get_vsi_from_adapter(struct i40e_adapter *adapter)
> return NULL;
>
> hw = I40E_DEV_PRIVATE_TO_HW(adapter);
> +#ifdef X722_SUPPORT
> if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
> +#else
> + if (hw->mac.type == I40E_MAC_VF) {
> +#endif /* X722_SUPPORT */
> struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(adapter);
> return &vf->vsi;
> } else {
> diff --git a/drivers/net/i40e/i40e_ethdev_vf.c b/drivers/net/i40e/i40e_ethdev_vf.c
> index 34eb274..aab9cae 100644
> --- a/drivers/net/i40e/i40e_ethdev_vf.c
> +++ b/drivers/net/i40e/i40e_ethdev_vf.c
> @@ -1112,9 +1112,17 @@ i40evf_get_link_status(struct rte_eth_dev *dev, struct rte_eth_link *link)
> static const struct rte_pci_id pci_id_i40evf_map[] = {
> { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF) },
> { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF_HV) },
> +#ifdef X722_SUPPORT
> +#ifdef X722_A0_SUPPORT
> +#if defined(INTEGRATED_VF) || defined(VF_DRIVER)
> { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0_VF) },
> +#endif /* INTEGRATED_VF || VF_DRIVER */
> +#endif /* X722_A0_SUPPORT */
> +#if defined(INTEGRATED_VF) || defined(VF_DRIVER) || defined(I40E_NDIS_SUPPORT)
> { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF) },
> { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF_HV) },
> +#endif /* INTEGRATED_VF || VF_DRIVER || I40E_NDIS_SUPPORT */
> +#endif /* X722_SUPPORT */
> { .vendor_id = 0, /* sentinel */ },
> };
>
> @@ -1277,8 +1285,10 @@ i40evf_init_vf(struct rte_eth_dev *dev)
> goto err_alloc;
> }
>
> +#ifdef X722_SUPPORT
> if (hw->mac.type == I40E_MAC_X722_VF)
> vf->flags = I40E_FLAG_RSS_AQ_CAPABLE;
> +#endif /* X722_SUPPORT */
> vf->vsi.vsi_id = vf->vsi_res->vsi_id;
> vf->vsi.type = vf->vsi_res->vsi_type;
> vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;
> @@ -2340,6 +2350,7 @@ i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
> if (!lut)
> return -EINVAL;
>
> +#ifdef X722_SUPPORT
> if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
> ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, FALSE,
> lut, lut_size);
> @@ -2348,12 +2359,15 @@ i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
> return ret;
> }
> } else {
> +#endif /* X722_SUPPORT */
> uint32_t *lut_dw = (uint32_t *)lut;
> uint16_t i, lut_size_dw = lut_size / 4;
>
> for (i = 0; i < lut_size_dw; i++)
> lut_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HLUT(i));
> +#ifdef X722_SUPPORT
> }
> +#endif /* X722_SUPPORT */
>
> return 0;
> }
> @@ -2371,6 +2385,7 @@ i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
> vf = I40E_VSI_TO_VF(vsi);
> hw = I40E_VSI_TO_HW(vsi);
>
> +#ifdef X722_SUPPORT
> if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
> ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE,
> lut, lut_size);
> @@ -2379,13 +2394,16 @@ i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
> return ret;
> }
> } else {
> +#endif /* X722_SUPPORT */
> uint32_t *lut_dw = (uint32_t *)lut;
> uint16_t i, lut_size_dw = lut_size / 4;
>
> for (i = 0; i < lut_size_dw; i++)
> I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i), lut_dw[i]);
> I40EVF_WRITE_FLUSH(hw);
> +#ifdef X722_SUPPORT
> }
> +#endif /* X722_SUPPORT */
>
> return 0;
> }
> @@ -2484,6 +2502,7 @@ i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
> return -EINVAL;
> }
>
> +#ifdef X722_SUPPORT
> if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
> struct i40e_aqc_get_set_rss_key_data *key_dw =
> (struct i40e_aqc_get_set_rss_key_data *)key;
> @@ -2493,13 +2512,16 @@ i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
> PMD_INIT_LOG(ERR, "Failed to configure RSS key "
> "via AQ");
> } else {
> +#endif /* X722_SUPPORT */
> uint32_t *hash_key = (uint32_t *)key;
> uint16_t i;
>
> for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
> i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]);
> I40EVF_WRITE_FLUSH(hw);
> +#ifdef X722_SUPPORT
> }
> +#endif /* X722_SUPPORT */
>
> return ret;
> }
> @@ -2514,6 +2536,7 @@ i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
> if (!key || !key_len)
> return -EINVAL;
>
> +#ifdef X722_SUPPORT
> if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
> ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
> (struct i40e_aqc_get_set_rss_key_data *)key);
> @@ -2522,12 +2545,16 @@ i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
> return ret;
> }
> } else {
> +#endif /* X722_SUPPORT */
> uint32_t *key_dw = (uint32_t *)key;
> uint16_t i;
>
> for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
> key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i));
> +#ifdef X722_SUPPORT
> }
> +#endif /* X722_SUPPORT */
> +
> *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
>
> return 0;
> diff --git a/drivers/net/i40e/i40e_regs.h b/drivers/net/i40e/i40e_regs.h
> index 472c7a0..7be6ce3 100644
> --- a/drivers/net/i40e/i40e_regs.h
> +++ b/drivers/net/i40e/i40e_regs.h
> @@ -52,7 +52,9 @@ static const struct i40e_reg_info i40e_regs_adminq[] = {
> {I40E_VSILAN_QBASE(0), 383, 4, 0, 0, "VSILAN_QBASE"},
> {I40E_VSIQF_CTL(0), 383, 4, 0, 0, "VSIQF_CTL"},
> {I40E_PFQF_HKEY(0), 12, 128, 0, 0, "PFQF_HKEY"},
> +#ifdef X722_SUPPORT
> {I40E_PFQF_HREGION(0), 7, 128, 0, 0, "PFQF_HREGION"},
> +#endif
> {I40E_PFQF_HENA(0), 1, 128, 0, 0, "PFQF_HENA"},
> {I40E_PFQF_FDALLOC, 0, 0, 0, 0, "PFQF_FDALLOC"},
> {I40E_PRTQF_FD_INSET(0, 0), 63, 64, 1, 32, "PRTQF_FD_INSET"},
> @@ -60,9 +62,11 @@ static const struct i40e_reg_info i40e_regs_adminq[] = {
> {I40E_PRTQF_FD_MSK(0, 0), 63, 64, 1, 32, "PRTQF_FD_MSK"},
> {I40E_PRTQF_FD_FLXINSET(0), 63, 32, 0, 0, "PRTQF_FD_FLXINSET"},
> {I40E_PRTQF_CTL_0, 0, 0, 0, 0, "PRTQF_CTL_0"},
> +#ifdef X722_SUPPORT
> {I40E_GLQF_FD_MSK(0, 0), 1, 4, 63, 8, "GLQF_FD_MSK"},
> {I40E_GLQF_HASH_INSET(0, 0), 1, 4, 63, 8, "GLQF_HASH_INSET"},
> {I40E_GLQF_HASH_MSK(0, 0), 1, 4, 63, 8, "GLQF_HASH_MSK"},
> +#endif
> {I40E_GLQF_SWAP(0, 0), 1, 4, 63, 8, "GLQF_SWAP"},
> {I40E_GLFCOE_RCTL, 0, 0, 0, 0, "GLFCOE_RCTL"},
> {I40E_GLQF_CTL, 0, 0, 0, 0, "GLQF_CTL"},
> @@ -72,6 +76,7 @@ static const struct i40e_reg_info i40e_regs_adminq[] = {
>
> static const struct i40e_reg_info i40e_regs_others[] = {
> {I40E_QTX_TAIL1(0), 15, 4, 0, 0, "QTX_TAIL1"},
> +#ifdef X722_SUPPORT
> {I40E_VFPE_CQPDB(0), 127, 4, 0, 0, "VFPE_CQPDB"},
> {I40E_VFPE_CQPTAIL(0), 127, 4, 0, 0, "VFPE_CQPTAIL"},
> {I40E_VFPE_CCQPSTATUS(0), 127, 4, 0, 0, "VFPE_CCQPSTATUS"},
> @@ -79,12 +84,15 @@ static const struct i40e_reg_info i40e_regs_others[] = {
> {I40E_VFPE_CCQPHIGH(0), 127, 4, 0, 0, "VFPE_CCQPHIGH"},
> {I40E_VFPE_IPCONFIG0(0), 127, 4, 0, 0, "VFPE_IPCONFIG0"},
> {I40E_VFPE_CQPERRCODES(0), 127, 4, 0, 0, "VFPE_CQPERRCODES"},
> +#endif
> {I40E_QRX_TAIL1(0), 15, 4, 0, 0, "QRX_TAIL1"},
> {I40E_VFINT_ITRN1(0, 0), 2, 64, 15, 4, "VFINT_ITRN1"},
> +#ifdef X722_SUPPORT
> {I40E_VFPE_TCPNOWTIMER(0), 127, 4, 0, 0, "VFPE_TCPNOWTIMER"},
> {I40E_VFPE_MRTEIDXMASK(0), 127, 4, 0, 0, "VFPE_MRTEIDXMASK"},
> {I40E_VFPE_RCVUNEXPECTEDERROR(0), 127, 4, 0, 0,
> "VFPE_RCVUNEXPECTEDERROR"},
> +#endif
> {I40E_VFINT_DYN_CTLN1(0), 15, 4, 0, 0, "VFINT_DYN_CTLN1"},
> {I40E_VFINT_ICR01, 0, 0, 0, 0, "VFINT_ICR01"},
> {I40E_VFINT_ITR01(0), 2, 4, 0, 0, "VFINT_ITR01"},
> @@ -100,19 +108,24 @@ static const struct i40e_reg_info i40e_regs_others[] = {
> {I40E_VF_ATQBAH1, 0, 0, 0, 0, "VF_ATQBAH1"},
> {I40E_VF_ATQBAL1, 0, 0, 0, 0, "VF_ATQBAL1"},
> {I40E_VF_ARQLEN1, 0, 0, 0, 0, "VF_ARQLEN1"},
> +#ifdef X722_SUPPORT
> {I40E_PFPE_CQPDB, 0, 0, 0, 0, "PFPE_CQPDB"},
> {I40E_PFPE_CQPTAIL, 0, 0, 0, 0, "PFPE_CQPTAIL"},
> {I40E_PFPE_CCQPSTATUS, 0, 0, 0, 0, "PFPE_CCQPSTATUS"},
> {I40E_PFPE_CCQPLOW, 0, 0, 0, 0, "PFPE_CCQPLOW"},
> {I40E_PFPE_CCQPHIGH, 0, 0, 0, 0, "PFPE_CCQPHIGH"},
> {I40E_PFPE_IPCONFIG0, 0, 0, 0, 0, "PFPE_IPCONFIG0"},
> +#endif
> {I40E_VF_ATQT1, 0, 0, 0, 0, "VF_ATQT1"},
> +#ifdef X722_SUPPORT
> {I40E_PFPE_TCPNOWTIMER, 0, 0, 0, 0, "PFPE_TCPNOWTIMER"},
> {I40E_PFPE_MRTEIDXMASK, 0, 0, 0, 0, "PFPE_MRTEIDXMASK"},
> {I40E_PFPE_RCVUNEXPECTEDERROR, 0, 0, 0, 0, "PFPE_RCVUNEXPECTEDERROR"},
> {I40E_PFPE_UDACTRL, 0, 0, 0, 0, "PFPE_UDACTRL"},
> {I40E_PFPE_UDAUCFBQPN, 0, 0, 0, 0, "PFPE_UDAUCFBQPN"},
> +#endif
> {I40E_VFGEN_RSTAT, 0, 0, 0, 0, "VFGEN_RSTAT"},
> +#ifdef X722_SUPPORT
> {I40E_PFPE_CQPERRCODES, 0, 0, 0, 0, "PFPE_CQPERRCODES"},
> {I40E_PFPE_FLMXMITALLOCERR, 0, 0, 0, 0, "PFPE_FLMXMITALLOCERR"},
> {I40E_PFPE_FLMQ1ALLOCERR, 0, 0, 0, 0, "PFPE_FLMQ1ALLOCERR"},
> @@ -134,7 +147,9 @@ static const struct i40e_reg_info i40e_regs_others[] = {
> {I40E_GLPE_VFUDAUCFBQPN(0), 31, 4, 0, 0, "GLPE_VFUDAUCFBQPN"},
> {I40E_GLPE_VFFLMXMITALLOCERR(0), 31, 4, 0, 0, "GLPE_VFFLMXMITALLOCERR"},
> {I40E_GLPE_VFFLMQ1ALLOCERR(0), 31, 4, 0, 0, "GLPE_VFFLMQ1ALLOCERR"},
> +#endif
> {I40E_VFQF_HLUT(0), 15, 4, 0, 0, "VFQF_HLUT"},
> +#ifdef X722_SUPPORT
> {I40E_GLPE_CPUSTATUS0, 0, 0, 0, 0, "GLPE_CPUSTATUS0"},
> {I40E_GLPE_CPUSTATUS1, 0, 0, 0, 0, "GLPE_CPUSTATUS1"},
> {I40E_GLPE_CPUSTATUS2, 0, 0, 0, 0, "GLPE_CPUSTATUS2"},
> @@ -158,8 +173,10 @@ static const struct i40e_reg_info i40e_regs_others[] = {
> {I40E_PRTPE_RUPM_CNTR, 0, 0, 0, 0, "PRTPE_RUPM_CNTR"},
> {I40E_PRTPE_RUPM_PTXTCCNTR03, 0, 0, 0, 0, "PRTPE_RUPM_PTXTCCNTR03"},
> {I40E_PRTPE_RUPM_PTCTCCNTR47, 0, 0, 0, 0, "PRTPE_RUPM_PTCTCCNTR47"},
> +#endif
> {I40E_VFCM_PE_ERRDATA, 0, 0, 0, 0, "VFCM_PE_ERRDATA"},
> {I40E_PFPCI_VF_FLUSH_DONE, 0, 0, 0, 0, "PFPCI_VF_FLUSH_DONE"},
> +#ifdef X722_SUPPORT
> {I40E_GLPES_PFRXVLANERR(0), 15, 4, 0, 0, "GLPES_PFRXVLANERR"},
> {I40E_GLPES_PFIP4RXOCTSLO(0), 15, 8, 0, 0, "GLPES_PFIP4RXOCTSLO"},
> {I40E_GLPES_PFIP4RXOCTSHI(0), 15, 8, 0, 0, "GLPES_PFIP4RXOCTSHI"},
> @@ -333,6 +350,7 @@ static const struct i40e_reg_info i40e_regs_others[] = {
> {I40E_PRTDCB_TCMSTC_RLPM(0), 7, 32, 0, 0, "PRTDCB_TCMSTC_RLPM"},
> {I40E_PRTDCB_RLPMC, 0, 0, 0, 0, "PRTDCB_RLPMC"},
> {I40E_PRTDCB_TCPMC_RLPM, 0, 0, 0, 0, "PRTDCB_TCPMC_RLPM"},
> +#endif
> {I40E_VFINT_ITRN(0, 0), 2, 2048, 511, 4, "VFINT_ITRN"},
> {I40E_VFINT_DYN_CTLN(0), 511, 4, 0, 0, "VFINT_DYN_CTLN"},
> {I40E_VPINT_LNKLSTN(0), 511, 4, 0, 0, "VPINT_LNKLSTN"},
> @@ -376,7 +394,9 @@ static const struct i40e_reg_info i40e_regs_others[] = {
> {I40E_VPLAN_QTABLE(0, 0), 15, 1024, 127, 4, "VPLAN_QTABLE"},
> {I40E_VPLAN_MAPENA(0), 127, 4, 0, 0, "VPLAN_MAPENA"},
> {I40E_VFGEN_RSTAT1(0), 127, 4, 0, 0, "VFGEN_RSTAT1"},
> +#ifdef X722_SUPPORT
> {I40E_VPLAN_QBASE(0), 127, 4, 0, 0, "VPLAN_QBASE"},
> +#endif
> {I40E_PF_ATQBAL, 0, 0, 0, 0, "PF_ATQBAL"},
> {I40E_GL_ATQBAL, 0, 0, 0, 0, "GL_ATQBAL"},
> {I40E_PF_ARQBAL, 0, 0, 0, 0, "PF_ARQBAL"},
> @@ -411,8 +431,10 @@ static const struct i40e_reg_info i40e_regs_others[] = {
> {I40E_GLDCB_GENC, 0, 0, 0, 0, "GLDCB_GENC"},
> {I40E_GL_FWSTS, 0, 0, 0, 0, "GL_FWSTS"},
> {I40E_GL_FWRESETCNT, 0, 0, 0, 0, "GL_FWRESETCNT"},
> +#ifdef X722_SUPPORT
> {I40E_GL_VF_CTRL_TX(0), 127, 4, 0, 0, "GL_VF_CTRL_TX"},
> {I40E_GL_VF_CTRL_RX(0), 127, 4, 0, 0, "GL_VF_CTRL_RX"},
> +#endif
> {I40E_PRTTSYN_CTL1, 0, 0, 0, 0, "PRTTSYN_CTL1"},
> {I40E_PRTTSYN_RXTIME_H(0), 3, 32, 0, 0, "PRTTSYN_RXTIME_H"},
> {I40E_PRTTSYN_RXTIME_L(0), 3, 32, 0, 0, "PRTTSYN_RXTIME_L"},
> @@ -420,10 +442,14 @@ static const struct i40e_reg_info i40e_regs_others[] = {
> {I40E_PRT_MNG_FTFT_MASK(0), 7, 32, 0, 0, "PRT_MNG_FTFT_MASK"},
> {I40E_PRT_MNG_FTFT_LENGTH, 0, 0, 0, 0, "PRT_MNG_FTFT_LENGTH"},
> {I40E_PRT_MNG_FTFT_DATA(0), 31, 32, 0, 0, "PRT_MNG_FTFT_DATA"},
> +#ifdef X722_SUPPORT
> {I40E_GL_PPRS_SPARE, 0, 0, 0, 0, "GL_PPRS_SPARE"},
> +#endif
> {I40E_PFGEN_STATE, 0, 0, 0, 0, "PFGEN_STATE"},
> {I40E_PFINT_GPIO_ENA, 0, 0, 0, 0, "PFINT_GPIO_ENA"},
> +#ifdef X722_SUPPORT
> {I40E_GLGEN_MISC_SPARE, 0, 0, 0, 0, "GLGEN_MISC_SPARE"},
> +#endif
> {I40E_GLGEN_GPIO_CTL(0), 29, 4, 0, 0, "GLGEN_GPIO_CTL"},
> {I40E_GLGEN_LED_CTL, 0, 0, 0, 0, "GLGEN_LED_CTL"},
> {I40E_GLGEN_GPIO_STAT, 0, 0, 0, 0, "GLGEN_GPIO_STAT"},
> @@ -470,6 +496,7 @@ static const struct i40e_reg_info i40e_regs_others[] = {
> {I40E_GLPCI_PM_MUX_NPQ, 0, 0, 0, 0, "GLPCI_PM_MUX_NPQ"},
> {I40E_GLPCI_SPARE_BITS_0, 0, 0, 0, 0, "GLPCI_SPARE_BITS_0"},
> {I40E_GLPCI_SPARE_BITS_1, 0, 0, 0, 0, "GLPCI_SPARE_BITS_1"},
> +#ifdef X722_SUPPORT
> {I40E_GLPCI_CUR_RLAN_ALWD, 0, 0, 0, 0, "GLPCI_CUR_RLAN_ALWD"},
> {I40E_GLPCI_CUR_TLAN_ALWD, 0, 0, 0, 0, "GLPCI_CUR_TLAN_ALWD"},
> {I40E_GLPCI_CUR_RXPE_ALWD, 0, 0, 0, 0, "GLPCI_CUR_RXPE_ALWD"},
> @@ -484,9 +511,11 @@ static const struct i40e_reg_info i40e_regs_others[] = {
> {I40E_GLPCI_CUR_PMAT_RSVD, 0, 0, 0, 0, "GLPCI_CUR_PMAT_RSVD"},
> {I40E_GLPCI_CUR_MNG_RSVD, 0, 0, 0, 0, "GLPCI_CUR_MNG_RSVD"},
> {I40E_GLPCI_CUR_TDPU_RSVD, 0, 0, 0, 0, "GLPCI_CUR_TDPU_RSVD"},
> +#endif
> {I40E_PFPCI_VF_FLUSH_DONE1(0), 127, 4, 0, 0, "PFPCI_VF_FLUSH_DONE1"},
> {I40E_PFPCI_PF_FLUSH_DONE, 0, 0, 0, 0, "PFPCI_PF_FLUSH_DONE"},
> {I40E_PFPCI_VM_FLUSH_DONE, 0, 0, 0, 0, "PFPCI_VM_FLUSH_DONE"},
> +#ifdef X722_SUPPORT
> {I40E_GLPCI_NPQ_CFG, 0, 0, 0, 0, "GLPCI_NPQ_CFG"},
> {I40E_GLPCI_CUR_CLNT_COMMON, 0, 0, 0, 0, "GLPCI_CUR_CLNT_COMMON"},
> {I40E_GLPCI_CUR_CLNT_PIPEMON, 0, 0, 0, 0, "GLPCI_CUR_CLNT_PIPEMON"},
> @@ -501,15 +530,20 @@ static const struct i40e_reg_info i40e_regs_others[] = {
> {I40E_GLPCI_WATMK_PMAT_ALWD, 0, 0, 0, 0, "GLPCI_WATMK_PMAT_ALWD"},
> {I40E_GLPCI_WATMK_MNG_ALWD, 0, 0, 0, 0, "GLPCI_WATMK_MNG_ALWD"},
> {I40E_GLPCI_WATMK_TPDU_ALWD, 0, 0, 0, 0, "GLPCI_WATMK_TPDU_ALWD"},
> +#endif
> {I40E_PRTDCB_TCMSTC(0), 7, 32, 0, 0, "PRTDCB_TCMSTC"},
> +#ifdef X722_SUPPORT
> {I40E_PRTDCB_TFMSTC(0), 7, 32, 0, 0, "PRTDCB_TFMSTC"},
> +#endif
> {I40E_PRTDCB_TDPMC, 0, 0, 0, 0, "PRTDCB_TDPMC"},
> {I40E_PRTDCB_TCWSTC(0), 7, 32, 0, 0, "PRTDCB_TCWSTC"},
> {I40E_PRTDCB_TCPMC, 0, 0, 0, 0, "PRTDCB_TCPMC"},
> +#ifdef X722_SUPPORT
> {I40E_GL_TUPM_SPARE, 0, 0, 0, 0, "GL_TUPM_SPARE"},
> {I40E_GLPEOC_CACHESIZE, 0, 0, 0, 0, "GLPEOC_CACHESIZE"},
> {I40E_GLPBLOC_CACHESIZE, 0, 0, 0, 0, "GLPBLOC_CACHESIZE"},
> {I40E_GLFOC_CACHESIZE, 0, 0, 0, 0, "GLFOC_CACHESIZE"},
> +#endif
> {I40E_PRTRPB_DHW(0), 7, 32, 0, 0, "PRTRPB_DHW"},
> {I40E_PRTRPB_DLW(0), 7, 32, 0, 0, "PRTRPB_DLW"},
> {I40E_PRTRPB_DPS(0), 7, 32, 0, 0, "PRTRPB_DPS"},
> @@ -536,6 +570,7 @@ static const struct i40e_reg_info i40e_regs_others[] = {
> {I40E_GLGEN_STAT, 0, 0, 0, 0, "GLGEN_STAT"},
> {I40E_GL_MNG_HWARB_CTRL, 0, 0, 0, 0, "GL_MNG_HWARB_CTRL"},
> {I40E_GL_MNG_FWSM, 0, 0, 0, 0, "GL_MNG_FWSM"},
> +#ifdef X722_SUPPORT
> {I40E_GLNVM_ALTIMERS, 0, 0, 0, 0, "GLNVM_ALTIMERS"},
> {I40E_GLNVM_ULT, 0, 0, 0, 0, "GLNVM_ULT"},
> {I40E_MEM_INIT_DONE_STAT, 0, 0, 0, 0, "MEM_INIT_DONE_STAT"},
> @@ -553,6 +588,7 @@ static const struct i40e_reg_info i40e_regs_others[] = {
> {I40E_MNGSB_WDATA, 0, 0, 0, 0, "MNGSB_WDATA"},
> {I40E_MNGSB_RHDR0, 0, 0, 0, 0, "MNGSB_RHDR0"},
> {I40E_MNGSB_RDATA, 0, 0, 0, 0, "MNGSB_RDATA"},
> +#endif
> {I40E_PFPM_APM, 0, 0, 0, 0, "PFPM_APM"},
> {I40E_PRTGEN_STATUS, 0, 0, 0, 0, "PRTGEN_STATUS"},
> {I40E_PRTGEN_CNF, 0, 0, 0, 0, "PRTGEN_CNF"},
> @@ -562,8 +598,10 @@ static const struct i40e_reg_info i40e_regs_others[] = {
> {I40E_GLGEN_CLKSTAT, 0, 0, 0, 0, "GLGEN_CLKSTAT"},
> {I40E_GLGEN_RSTAT, 0, 0, 0, 0, "GLGEN_RSTAT"},
> {I40E_GLGEN_RTRIG, 0, 0, 0, 0, "GLGEN_RTRIG"},
> +#ifdef X722_SUPPORT
> {I40E_GLGEN_PME_TO, 0, 0, 0, 0, "GLGEN_PME_TO"},
> {I40E_GLGEN_CAR_DEBUG, 0, 0, 0, 0, "GLGEN_CAR_DEBUG"},
> +#endif
> {I40E_PFPCI_CNF, 0, 0, 0, 0, "PFPCI_CNF"},
> {I40E_PFPCI_DEVID, 0, 0, 0, 0, "PFPCI_DEVID"},
> {I40E_PFPCI_SUBSYSID, 0, 0, 0, 0, "PFPCI_SUBSYSID"},
> @@ -589,7 +627,9 @@ static const struct i40e_reg_info i40e_regs_others[] = {
> {I40E_GLPCI_UPADD, 0, 0, 0, 0, "GLPCI_UPADD"},
> {I40E_GLPCI_PCIERR, 0, 0, 0, 0, "GLPCI_PCIERR"},
> {I40E_GLPCI_VENDORID, 0, 0, 0, 0, "GLPCI_VENDORID"},
> +#ifdef X722_SUPPORT
> {I40E_GL_UFUSE_SOC, 0, 0, 0, 0, "GL_UFUSE_SOC"},
> +#endif
> {I40E_PFHMC_SDCMD, 0, 0, 0, 0, "PFHMC_SDCMD"},
> {I40E_PFHMC_SDDATALOW, 0, 0, 0, 0, "PFHMC_SDDATALOW"},
> {I40E_PFHMC_SDDATAHIGH, 0, 0, 0, 0, "PFHMC_SDDATAHIGH"},
> @@ -597,7 +637,9 @@ static const struct i40e_reg_info i40e_regs_others[] = {
> {I40E_PFHMC_ERRORINFO, 0, 0, 0, 0, "PFHMC_ERRORINFO"},
> {I40E_PFHMC_ERRORDATA, 0, 0, 0, 0, "PFHMC_ERRORDATA"},
> {I40E_GLHMC_SDPART(0), 15, 4, 0, 0, "GLHMC_SDPART"},
> +#ifdef X722_SUPPORT
> {I40E_GLHMC_PFPESDPART(0), 15, 4, 0, 0, "GLHMC_PFPESDPART"},
> +#endif
> {I40E_GLHMC_PFASSIGN(0), 15, 4, 0, 0, "GLHMC_PFASSIGN"},
> {I40E_GLHMC_LANTXOBJSZ, 0, 0, 0, 0, "GLHMC_LANTXOBJSZ"},
> {I40E_GLHMC_LANQMAX, 0, 0, 0, 0, "GLHMC_LANQMAX"},
> @@ -605,6 +647,7 @@ static const struct i40e_reg_info i40e_regs_others[] = {
> {I40E_GLHMC_FCOEDDPOBJSZ, 0, 0, 0, 0, "GLHMC_FCOEDDPOBJSZ"},
> {I40E_GLHMC_FCOEMAX, 0, 0, 0, 0, "GLHMC_FCOEMAX"},
> {I40E_GLHMC_FCOEFOBJSZ, 0, 0, 0, 0, "GLHMC_FCOEFOBJSZ"},
> +#ifdef X722_SUPPORT
> {I40E_GLHMC_PEQPOBJSZ, 0, 0, 0, 0, "GLHMC_PEQPOBJSZ"},
> {I40E_GLHMC_PECQOBJSZ, 0, 0, 0, 0, "GLHMC_PECQOBJSZ"},
> {I40E_GLHMC_PESRQOBJSZ, 0, 0, 0, 0, "GLHMC_PESRQOBJSZ"},
> @@ -621,10 +664,12 @@ static const struct i40e_reg_info i40e_regs_others[] = {
> {I40E_GLHMC_PEQ1OBJSZ, 0, 0, 0, 0, "GLHMC_PEQ1OBJSZ"},
> {I40E_GLHMC_PEQ1MAX, 0, 0, 0, 0, "GLHMC_PEQ1MAX"},
> {I40E_GLHMC_PEQ1FLMAX, 0, 0, 0, 0, "GLHMC_PEQ1FLMAX"},
> +#endif
> {I40E_GLHMC_FSIMCOBJSZ, 0, 0, 0, 0, "GLHMC_FSIMCOBJSZ"},
> {I40E_GLHMC_FSIMCMAX, 0, 0, 0, 0, "GLHMC_FSIMCMAX"},
> {I40E_GLHMC_FSIAVOBJSZ, 0, 0, 0, 0, "GLHMC_FSIAVOBJSZ"},
> {I40E_GLHMC_FSIAVMAX, 0, 0, 0, 0, "GLHMC_FSIAVMAX"},
> +#ifdef X722_SUPPORT
> {I40E_GLHMC_PEPBLMAX, 0, 0, 0, 0, "GLHMC_PEPBLMAX"},
> {I40E_GLHMC_PETIMEROBJSZ, 0, 0, 0, 0, "GLHMC_PETIMEROBJSZ"},
> {I40E_GLHMC_PETIMERMAX, 0, 0, 0, 0, "GLHMC_PETIMERMAX"},
> @@ -695,11 +740,14 @@ static const struct i40e_reg_info i40e_regs_others[] = {
> {I40E_GLHMC_VFPETIMERBASE(0), 31, 4, 0, 0, "GLHMC_VFPETIMERBASE"},
> {I40E_GLHMC_VFPETIMERCNT(0), 31, 4, 0, 0, "GLHMC_VFPETIMERCNT"},
> {I40E_GLPDOC_CACHESIZE, 0, 0, 0, 0, "GLPDOC_CACHESIZE"},
> +#endif
> {I40E_QTX_HEAD(0), 1535, 4, 0, 0, "QTX_HEAD"},
> {I40E_VP_MDET_TX(0), 127, 4, 0, 0, "VP_MDET_TX"},
> {I40E_PF_MDET_TX, 0, 0, 0, 0, "PF_MDET_TX"},
> {I40E_GL_MDET_TX, 0, 0, 0, 0, "GL_MDET_TX"},
> +#ifdef X722_SUPPORT
> {I40E_GL_TLAN_SPARE, 0, 0, 0, 0, "GL_TLAN_SPARE"},
> +#endif
> {I40E_GLLAN_TXPRE_QDIS(0), 11, 4, 0, 0, "GLLAN_TXPRE_QDIS"},
> {I40E_QTX_ENA(0), 1535, 4, 0, 0, "QTX_ENA"},
> {I40E_QTX_CTL(0), 1535, 4, 0, 0, "QTX_CTL"},
> @@ -709,7 +757,9 @@ static const struct i40e_reg_info i40e_regs_others[] = {
> {I40E_PFCM_LANCTXDATA(0), 3, 128, 0, 0, "PFCM_LANCTXDATA"},
> {I40E_PFCM_LANCTXCTL, 0, 0, 0, 0, "PFCM_LANCTXCTL"},
> {I40E_PFCM_LANCTXSTAT, 0, 0, 0, 0, "PFCM_LANCTXSTAT"},
> +#ifdef X722_SUPPORT
> {I40E_GLCM_LAN_CACHESIZE, 0, 0, 0, 0, "GLCM_LAN_CACHESIZE"},
> +#endif
> {I40E_QRX_ENA(0), 1535, 4, 0, 0, "QRX_ENA"},
> {I40E_PRTDCB_RETSTCC(0), 7, 32, 0, 0, "PRTDCB_RETSTCC"},
> {I40E_PRTDCB_RPPMC, 0, 0, 0, 0, "PRTDCB_RPPMC"},
> @@ -721,6 +771,7 @@ static const struct i40e_reg_info i40e_regs_others[] = {
> {I40E_PF_MDET_RX, 0, 0, 0, 0, "PF_MDET_RX"},
> {I40E_GLLAN_RCTL_0, 0, 0, 0, 0, "GLLAN_RCTL_0"},
> {I40E_GL_MDET_RX, 0, 0, 0, 0, "GL_MDET_RX"},
> +#ifdef X722_SUPPORT
> {I40E_VFPE_CQARM(0), 127, 4, 0, 0, "VFPE_CQARM"},
> {I40E_VFPE_CQACK(0), 127, 4, 0, 0, "VFPE_CQACK"},
> {I40E_VFPE_AEQALLOC(0), 127, 4, 0, 0, "VFPE_AEQALLOC"},
> @@ -738,14 +789,17 @@ static const struct i40e_reg_info i40e_regs_others[] = {
> {I40E_GLPE_VFCEQEDROPCNT(0), 31, 4, 0, 0, "GLPE_VFCEQEDROPCNT"},
> {I40E_GLPE_VFAEQEDROPCNT(0), 31, 4, 0, 0, "GLPE_VFAEQEDROPCNT"},
> {I40E_VFPE_WQEALLOC(0), 127, 4, 0, 0, "VFPE_WQEALLOC"},
> +#endif
> {I40E_VFCM_PE_ERRINFO1(0), 127, 4, 0, 0, "VFCM_PE_ERRINFO1"},
> {I40E_VFCM_PE_ERRDATA1(0), 127, 4, 0, 0, "VFCM_PE_ERRDATA1"},
> +#ifdef X722_SUPPORT
> {I40E_PFPE_WQEALLOC, 0, 0, 0, 0, "PFPE_WQEALLOC"},
> {I40E_PFCM_PE_ERRINFO, 0, 0, 0, 0, "PFCM_PE_ERRINFO"},
> {I40E_PFCM_PE_ERRDATA, 0, 0, 0, 0, "PFCM_PE_ERRDATA"},
> {I40E_GLHMC_DBQPPART(0), 15, 4, 0, 0, "GLHMC_DBQPPART"},
> {I40E_GLHMC_VFDBQPPART(0), 31, 4, 0, 0, "GLHMC_VFDBQPPART"},
> {I40E_GLCM_PE_CACHESIZE, 0, 0, 0, 0, "GLCM_PE_CACHESIZE"},
> +#endif
> {I40E_PFGEN_PORTNUM, 0, 0, 0, 0, "PFGEN_PORTNUM"},
> {I40E_PF_VT_PFALLOC, 0, 0, 0, 0, "PF_VT_PFALLOC"},
> {I40E_PRTDCB_TC2PFC, 0, 0, 0, 0, "PRTDCB_TC2PFC"},
> @@ -756,8 +810,10 @@ static const struct i40e_reg_info i40e_regs_others[] = {
> {I40E_PRTGL_SAL, 0, 0, 0, 0, "PRTGL_SAL"},
> {I40E_PRTGL_SAH, 0, 0, 0, 0, "PRTGL_SAH"},
> {I40E_PRTDCB_MFLCN, 0, 0, 0, 0, "PRTDCB_MFLCN"},
> +#ifdef X722_SUPPORT
> {I40E_PRTMAC_LINK_DOWN_COUNTER, 0, 0, 0, 0,
> "PRTMAC_LINK_DOWN_COUNTER"},
> +#endif
> {I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE, 0, 0, 0, 0,
> "PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE"},
> {I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE, 0, 0, 0, 0,
> @@ -817,12 +873,16 @@ static const struct i40e_reg_info i40e_regs_others[] = {
> {I40E_PRTDCB_FCCFG, 0, 0, 0, 0, "PRTDCB_FCCFG"},
> {I40E_PRTDCB_TPFCTS(0), 7, 32, 0, 0, "PRTDCB_TPFCTS"},
> {I40E_VFQF_HLUT1(0, 0), 15, 1024, 127, 4, "VFQF_HLUT1"},
> +#ifdef X722_SUPPORT
> {I40E_VSIQF_HLUT(0, 0), 15, 2048, 383, 4, "VSIQF_HLUT"},
> +#endif
> {I40E_VFQF_HKEY1(0, 0), 12, 1024, 127, 4, "VFQF_HKEY1"},
> {I40E_VFQF_HREGION1(0, 0), 7, 1024, 127, 4, "VFQF_HREGION1"},
> {I40E_VFQF_HENA1(0, 0), 1, 1024, 127, 4, "VFQF_HENA1"},
> {I40E_PFQF_HLUT(0), 127, 128, 0, 0, "PFQF_HLUT"},
> +#ifdef X722_SUPPORT
> {I40E_X722_PFQF_HLUT(0), 127, 128, 0, 0, "X722_PFQF_HLUT"},
> +#endif
> {I40E_PFQF_CTL_1, 0, 0, 0, 0, "PFQF_CTL_1"},
> {I40E_PFQF_FDSTAT, 0, 0, 0, 0, "PFQF_FDSTAT"},
> {I40E_PRT_MNG_MIPAF6(0), 15, 32, 0, 0, "PRT_MNG_MIPAF6"},
> @@ -839,21 +899,25 @@ static const struct i40e_reg_info i40e_regs_others[] = {
> {I40E_PRT_MNG_MANC, 0, 0, 0, 0, "PRT_MNG_MANC"},
> {I40E_PRT_MNG_MNGONLY, 0, 0, 0, 0, "PRT_MNG_MNGONLY"},
> {I40E_PRT_MNG_MSFM, 0, 0, 0, 0, "PRT_MNG_MSFM"},
> +#ifdef X722_SUPPORT
> {I40E_GLQF_APBVT(0), 2047, 4, 0, 0, "GLQF_APBVT"},
> {I40E_GLQF_PCNT(0), 511, 4, 0, 0, "GLQF_PCNT"},
> {I40E_GLQF_FD_PCTYPES(0), 63, 4, 0, 0, "GLQF_FD_PCTYPES"},
> {I40E_GLQF_ORT(0), 63, 4, 0, 0, "GLQF_ORT"},
> {I40E_GLQF_PIT(0), 23, 4, 0, 0, "GLQF_PIT"},
> +#endif
> {I40E_GL_PRS_FVBM(0), 3, 4, 0, 0, "GL_PRS_FVBM"},
> {I40E_GLQF_FDCNT_0, 0, 0, 0, 0, "GLQF_FDCNT_0"},
> {I40E_GL_MTG_FLU_MSK_H, 0, 0, 0, 0, "GL_MTG_FLU_MSK_H"},
> {I40E_GL_SWR_DEF_ACT_EN(0), 1, 4, 0, 0, "GL_SWR_DEF_ACT_EN"},
> {I40E_GLQF_HKEY(0), 12, 4, 0, 0, "GLQF_HKEY"},
> {I40E_GL_SWR_DEF_ACT(0), 35, 4, 0, 0, "GL_SWR_DEF_ACT"},
> +#ifdef X722_SUPPORT
> {I40E_GLQF_FDEVICTFLAG, 0, 0, 0, 0, "GLQF_FDEVICTFLAG"},
> {I40E_PFQF_CTL_2, 0, 0, 0, 0, "PFQF_CTL_2"},
> {I40E_GLQF_FDEVICTENA(0), 1, 4, 0, 0, "GLQF_FDEVICTENA"},
> {I40E_VSIQF_HKEY(0, 0), 12, 2048, 383, 4, "VSIQF_HKEY"},
> +#endif
> {I40E_GLPRT_GORCL(0), 3, 8, 0, 0, "GLPRT_GORCL"},
> {I40E_GLPRT_GORCH(0), 3, 8, 0, 0, "GLPRT_GORCH"},
> {I40E_GLPRT_MLFC(0), 3, 8, 0, 0, "GLPRT_MLFC"},
> @@ -991,7 +1055,39 @@ static const struct i40e_reg_info i40e_regs_others[] = {
> {I40E_GLVEBVL_MPCH(0), 127, 8, 0, 0, "GLVEBVL_MPCH"},
> {I40E_GLVEBVL_BPCL(0), 127, 8, 0, 0, "GLVEBVL_BPCL"},
> {I40E_GLVEBVL_BPCH(0), 127, 8, 0, 0, "GLVEBVL_BPCH"},
> +#ifdef X722_SUPPORT
> {I40E_GLGEN_STAT_HALT, 0, 0, 0, 0, "GLGEN_STAT_HALT"},
> {I40E_GLGEN_STAT_CLEAR, 0, 0, 0, 0, "GLGEN_STAT_CLEAR"},
> +#endif
> {0, 0, 0, 0, 0, NULL}
> };
> +
> +#ifndef X722_SUPPORT
> +#define I40E_GLQF_FD_MSK(_i, _j) \
> + (0x00267200 + ((_i) * 4 + (_j) * 8)) \
> + /* _i=0...1, _j=0...63 */ /* Reset: CORER */
> +#define I40E_GLQF_FD_MSK_MAX_INDEX 1
> +#define I40E_GLQF_FD_MSK_MASK_SHIFT 0
> +#define I40E_GLQF_FD_MSK_MASK_MASK \
> + I40E_MASK(0xFFFF, I40E_GLQF_FD_MSK_MASK_SHIFT)
> +#define I40E_GLQF_FD_MSK_OFFSET_SHIFT 16
> +#define I40E_GLQF_FD_MSK_OFFSET_MASK \
> + I40E_MASK(0x3F, I40E_GLQF_FD_MSK_OFFSET_SHIFT)
> +#define I40E_GLQF_HASH_INSET(_i, _j) \
> + (0x00267600 + ((_i) * 4 + (_j) * 8)) \
> + /* _i=0...1, _j=0...63 */ /* Reset: CORER */
> +#define I40E_GLQF_HASH_INSET_MAX_INDEX 1
> +#define I40E_GLQF_HASH_INSET_INSET_SHIFT 0
> +#define I40E_GLQF_HASH_INSET_INSET_MASK \
> + I40E_MASK(0xFFFFFFFF, I40E_GLQF_HASH_INSET_INSET_SHIFT)
> +#define I40E_GLQF_HASH_MSK(_i, _j) \
> + (0x00267A00 + ((_i) * 4 + (_j) * 8)) \
> + /* _i=0...1, _j=0...63 */ /* Reset: CORER */
> +#define I40E_GLQF_HASH_MSK_MAX_INDEX 1
> +#define I40E_GLQF_HASH_MSK_MASK_SHIFT 0
> +#define I40E_GLQF_HASH_MSK_MASK_MASK \
> + I40E_MASK(0xFFFF, I40E_GLQF_HASH_MSK_MASK_SHIFT)
> +#define I40E_GLQF_HASH_MSK_OFFSET_SHIFT 16
> +#define I40E_GLQF_HASH_MSK_OFFSET_MASK \
> + I40E_MASK(0x3F, I40E_GLQF_HASH_MSK_OFFSET_SHIFT)
> +#endif
> diff --git a/drivers/net/i40e/i40e_rxtx.c b/drivers/net/i40e/i40e_rxtx.c
> index 2cb2e30..4868786 100644
> --- a/drivers/net/i40e/i40e_rxtx.c
> +++ b/drivers/net/i40e/i40e_rxtx.c
> @@ -2199,7 +2199,11 @@ i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
> uint16_t base, bsf, tc_mapping;
> int use_def_burst_func = 1;
>
> +#ifdef X722_SUPPORT
> if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
> +#else
> + if (hw->mac.type == I40E_MAC_VF) {
> +#endif /* X722_SUPPORT */
> struct i40e_vf *vf =
> I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
> vsi = &vf->vsi;
> @@ -2239,7 +2243,12 @@ i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
> rxq->nb_rx_desc = nb_desc;
> rxq->rx_free_thresh = rx_conf->rx_free_thresh;
> rxq->queue_id = queue_idx;
> +
> +#ifdef X722_SUPPORT
> if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF)
> +#else
> + if (hw->mac.type == I40E_MAC_VF)
> +#endif /* X722_SUPPORT */
> rxq->reg_idx = queue_idx;
> else /* PF device */
> rxq->reg_idx = vsi->base_queue +
> @@ -2416,7 +2425,11 @@ i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
> uint16_t tx_rs_thresh, tx_free_thresh;
> uint16_t i, base, bsf, tc_mapping;
>
> +#ifdef X722_SUPPORT
> if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
> +#else
> + if (hw->mac.type == I40E_MAC_VF) {
> +#endif /* X722_SUPPORT */
> struct i40e_vf *vf =
> I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
> vsi = &vf->vsi;
> @@ -2544,12 +2557,15 @@ i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
> txq->hthresh = tx_conf->tx_thresh.hthresh;
> txq->wthresh = tx_conf->tx_thresh.wthresh;
> txq->queue_id = queue_idx;
> +#ifdef X722_SUPPORT
> if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF)
> +#else
> + if (hw->mac.type == I40E_MAC_VF)
> +#endif /* X722_SUPPORT */
> txq->reg_idx = queue_idx;
> else /* PF device */
> txq->reg_idx = vsi->base_queue +
> i40e_get_queue_offset_by_qindex(pf, queue_idx);
> -
> txq->port_id = dev->data->port_id;
> txq->txq_flags = tx_conf->txq_flags;
> txq->vsi = vsi;
> --
> 1.9.3
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