[dpdk-dev] [PATCH v2] net/i40e: set no drop for traffic class

Sexton, Rory rory.sexton at intel.com
Thu Jan 19 11:38:00 CET 2017


Perhaps the best solution is as suggested to set
rte_eth_conf.dcb_capability_en = ETH_DCB_PFC_SUPPORT
rte_eth_conf.rxmode.mq_mode = ETH_MQ_RX_DCB_FLAG
and set rte_eth_dcb_rx_conf.nb_tcs to the number of tc's to apply
Using this port configuration will give the same behavior of the patch and it removes the need for an API change.

Rory

-----Original Message-----
From: Wu, Jingjing 
Sent: Tuesday, January 17, 2017 3:09 PM
To: Sexton, Rory <rory.sexton at intel.com>
Cc: dev at dpdk.org; Marjanovic, Nemanja <nemanja.marjanovic at intel.com>
Subject: RE: [PATCH v2] net/i40e: set no drop for traffic class



> -----Original Message-----
> From: Sexton, Rory
> Sent: Monday, January 16, 2017 11:52 PM
> To: Wu, Jingjing <jingjing.wu at intel.com>
> Cc: dev at dpdk.org; Sexton, Rory <rory.sexton at intel.com>; Marjanovic, 
> Nemanja <nemanja.marjanovic at intel.com>
> Subject: [PATCH v2] net/i40e: set no drop for traffic class
> 
> From: Rory Sexton <rory.sexton at intel.com>
> 
> The default traffic class in i40e is set to drop versus on ixgbe it 
> isset to no drop. This means when packets build up in the RX SRAM on 
> the NIC, they are dropped, and they do this when the SW descriptor rings fill up.
> 
> This patch changes this behaviour and our testing shows there are no 
> drops as a result.
> 
> Signed-off-by: Rory Sexton <rory.sexton at intel.com>
> Signed-off-by: Nemanja Marjanovic <nemanja.marjanovic at intel.com>
> ---
> v2:
> * Changed to use existing api to set priority register directly.
> 
>  drivers/net/i40e/i40e_ethdev.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/net/i40e/i40e_ethdev.c 
> b/drivers/net/i40e/i40e_ethdev.c index 67778ba..97339b5 100644
> --- a/drivers/net/i40e/i40e_ethdev.c
> +++ b/drivers/net/i40e/i40e_ethdev.c
> @@ -2985,8 +2985,11 @@ static int
>  i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
>  			    __rte_unused struct rte_eth_pfc_conf *pfc_conf) {
> +	struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data-
> >dev_private);
> +
>  	PMD_INIT_FUNC_TRACE();
> 
> +	I40E_WRITE_REG(hw, I40E_PRTDCB_TC2PFC, 0xff);

PRTDCB_TC2PFC  is the Bitmap who controls the use of Priority Flow Control (PFC) per each TC. Bit n set to 1b indicates TC n uses PFC in Rx and Tx. The TC is referred as a no-drop TC.

And if look the rte_eth_pfc_conf, there is a field called priority, which would map to a TC.
Currently, the TC and priority is 1:1 map when dcb is enabled.
So how about change it like:
Check dcb info, and map the priority to tc, then val = 0x1 << tc; I40E_WRITE_REG(hw, I40E_PRTDCB_TC2PFC, val);

Thanks
Jingjing



>  	return -ENOSYS;
>  }
> 
> --
> 2.4.3

--------------------------------------------------------------
Intel Research and Development Ireland Limited
Registered in Ireland
Registered Office: Collinstown Industrial Park, Leixlip, County Kildare
Registered Number: 308263


This e-mail and any attachments may contain confidential material for the sole
use of the intended recipient(s). Any review or distribution by others is
strictly prohibited. If you are not the intended recipient, please contact the
sender and delete all copies.



More information about the dev mailing list