[dpdk-dev] [PATCH v2] ring: use aligned memzone allocation

[Jerin Jacob]

-----Original Message-----
> Date: Mon, 12 Jun 2017 10:18:39 +0000
> From: "Ananyev, Konstantin" <konstantin.ananyev at intel.com>
> To: Jerin Jacob <jerin.jacob at caviumnetworks.com>
> CC: Stephen Hemminger <stephen at networkplumber.org>, Yerden Zhumabekov
>  <e_zhumabekov at sts.kz>, "Richardson, Bruce" <bruce.richardson at intel.com>,
>  "Verkamp, Daniel" <daniel.verkamp at intel.com>, "dev at dpdk.org"
>  <dev at dpdk.org>
> Subject: RE: [dpdk-dev] [PATCH v2] ring: use aligned memzone allocation
> 
> 
> 
> > -----Original Message-----
> > From: Jerin Jacob [mailto:jerin.jacob at caviumnetworks.com]
> > Sent: Monday, June 12, 2017 4:08 AM
> > To: Ananyev, Konstantin <konstantin.ananyev at intel.com>
> > Cc: Stephen Hemminger <stephen at networkplumber.org>; Yerden Zhumabekov <e_zhumabekov at sts.kz>; Richardson, Bruce
> > <bruce.richardson at intel.com>; Verkamp, Daniel <daniel.verkamp at intel.com>; dev at dpdk.org
> > Subject: Re: [dpdk-dev] [PATCH v2] ring: use aligned memzone allocation
> > 
> > -----Original Message-----
> > > Date: Sat, 10 Jun 2017 08:16:44 +0000
> > > From: "Ananyev, Konstantin" <konstantin.ananyev at intel.com>
> > > To: Jerin Jacob <jerin.jacob at caviumnetworks.com>, Stephen Hemminger
> > >  <stephen at networkplumber.org>
> > > CC: Yerden Zhumabekov <e_zhumabekov at sts.kz>, "Richardson, Bruce"
> > >  <bruce.richardson at intel.com>, "Verkamp, Daniel"
> > >  <daniel.verkamp at intel.com>, "dev at dpdk.org" <dev at dpdk.org>
> > > Subject: RE: [dpdk-dev] [PATCH v2] ring: use aligned memzone allocation
> > >
> > >
> > >
> > > > -----Original Message-----
> > > > From: Jerin Jacob [mailto:jerin.jacob at caviumnetworks.com]
> > > > Sent: Friday, June 9, 2017 6:29 PM
> > > > To: Stephen Hemminger <stephen at networkplumber.org>
> > > > Cc: Yerden Zhumabekov <e_zhumabekov at sts.kz>; Ananyev, Konstantin <konstantin.ananyev at intel.com>; Richardson, Bruce
> > > > <bruce.richardson at intel.com>; Verkamp, Daniel <daniel.verkamp at intel.com>; dev at dpdk.org
> > > > Subject: Re: [dpdk-dev] [PATCH v2] ring: use aligned memzone allocation
> > > >
> > > > -----Original Message-----
> > > > > Date: Fri, 9 Jun 2017 10:16:25 -0700
> > > > > From: Stephen Hemminger <stephen at networkplumber.org>
> > > > > To: Yerden Zhumabekov <e_zhumabekov at sts.kz>
> > > > > Cc: "Ananyev, Konstantin" <konstantin.ananyev at intel.com>, "Richardson,
> > > > >  Bruce" <bruce.richardson at intel.com>, "Verkamp, Daniel"
> > > > >  <daniel.verkamp at intel.com>, "dev at dpdk.org" <dev at dpdk.org>
> > > > > Subject: Re: [dpdk-dev] [PATCH v2] ring: use aligned memzone allocation
> > > > >
> > > > > On Fri, 9 Jun 2017 18:47:43 +0600
> > > > > Yerden Zhumabekov <e_zhumabekov at sts.kz> wrote:
> > > > >
> > > > > > On 06.06.2017 19:19, Ananyev, Konstantin wrote:
> > > > > > >
> > > > > > >>>> Maybe there is some deeper  reason for the >= 128-byte alignment logic in rte_ring.h?
> > > > > > >>> Might be, would be good to hear opinion the author of that change.
> > > > > > >> It gives improved performance for core-2-core transfer.
> > > > > > > You mean empty cache-line(s) after prod/cons, correct?
> > > > > > > That's ok but why we can't keep them and whole rte_ring aligned on cache-line boundaries?
> > > > > > > Something like that:
> > > > > > > struct rte_ring {
> > > > > > >     ...
> > > > > > >     struct rte_ring_headtail prod __rte_cache_aligned;
> > > > > > >     EMPTY_CACHE_LINE   __rte_cache_aligned;
> > > > > > >     struct rte_ring_headtail cons __rte_cache_aligned;
> > > > > > >     EMPTY_CACHE_LINE   __rte_cache_aligned;
> > > > > > > };
> > > > > > >
> > > > > > > Konstantin
> > > > > > >
> > > > > >
> > > > > > I'm curious, can anyone explain, how does it actually affect
> > > > > > performance? Maybe we can utilize it application code?
> > > > >
> > > > > I think it is because on Intel CPU's the CPU will speculatively fetch adjacent cache lines.
> > > > > If these cache lines change, then it will create false sharing.
> > > >
> > > > I see. I think, In such cases it is better to abstract as conditional
> > > > compilation. The above logic has worst case cache memory
> > > > requirement if CPU is 128B CL and no speculative prefetch.
> 
> I suppose we can keep exactly the same logic as we have now:
> archs with 64B cache-line would have an empty cache line,
> for archs with 128B cacheline - no.
> Is that what you are looking for?

Its valid to an arch with 128B cache-line and speculative cache prefetch.
(Cavium's recent SoCs comes with this property)
IMHO, Instead of making 128B as NOOP. We can introduce a new conditional
compilation flag(CONFIG_RTE_ARCH_SPECULATIVE_PREFETCH or something like
that) to decide the empty line and I think, In future we can use
the same config for similar use cases.

Jerin

> Konstantin 
> 
> > >
> > > I think this is already done for rte_ring.h:
> > > http://dpdk.org/browse/dpdk/tree/lib/librte_ring/rte_ring.h#n119
> > 
> > Yes. The suggestion was in the context of when introducing the
> > EMPTY_CACHE_LINE scheme, it should be a function of ARCH has
> > speculative next cache-line prefetch or not?
> > 
> > >
> > > Konstantin
> > >
> > >
> > >