[dpdk-dev] [PATCH v2 5/7] net/mlx5: match Rx completion entry size to cacheline
Yongseok Koh
yskoh at mellanox.com
Mon Oct 9 20:46:58 CEST 2017
The size of Rx completion entry should match the size of a cacheline. This
is already reflected in struct mlx5_cqe by adding 64bytes padding if a
cacheline is 128bytes. Some ARM CPUs have 128bytes cacheline.
Signed-off-by: Yongseok Koh <yskoh at mellanox.com>
---
drivers/net/mlx5/mlx5.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c
index b2087c0ad..e1aa9b914 100644
--- a/drivers/net/mlx5/mlx5.c
+++ b/drivers/net/mlx5/mlx5.c
@@ -1012,6 +1012,9 @@ rte_mlx5_pmd_init(void)
setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
/* Don't map UAR to WC if BlueFlame is not used.*/
setenv("MLX5_SHUT_UP_BF", "1", 1);
+ /* Match the size of Rx completion entry to the size of a cacheline. */
+ if (RTE_CACHE_LINE_SIZE == 128)
+ setenv("MLX5_CQE_SIZE", "128", 0);
ibv_fork_init();
rte_pci_register(&mlx5_driver);
}
--
2.11.0
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