[dpdk-dev] [PATCH v3 3/6] net/i40e: implement dynamic mapping of sw flow types to hw pctypes
Xing, Beilei
beilei.xing at intel.com
Mon Sep 25 11:44:31 CEST 2017
> -----Original Message-----
> From: Rybalchenko, Kirill
> Sent: Wednesday, September 20, 2017 10:33 PM
> To: dev at dpdk.org
> Cc: Rybalchenko, Kirill <kirill.rybalchenko at intel.com>; Chilikin, Andrey
> <andrey.chilikin at intel.com>; Xing, Beilei <beilei.xing at intel.com>; Wu,
> Jingjing <jingjing.wu at intel.com>
> Subject: [PATCH v3 3/6] net/i40e: implement dynamic mapping of sw flow
> types to hw pctypes
>
> Implement dynamic mapping of software flow types to hardware pctypes.
> This allows to add new flow types and pctypes for DDP without changing API
> of the driver. The mapping table is located in private data area for particular
> network adapter and can be individually modified with set of appropriate
> functions.
>
> v2:
> Re-arrange patchset to avoid compillation errors.
> Remove usage of statically defined flow types and pctypes.
>
> v3:
> Changed prototypes of some static functions.
> Fixed bugs in i40e_pctype_to_flowtype and i40e_flowtype_to_pctype
> functions.
> Various small modifications after reviewing.
>
> Signed-off-by: Kirill Rybalchenko <kirill.rybalchenko at intel.com>
> ---
> drivers/net/i40e/i40e_ethdev.c | 343 ++++++++++++--------------------------
> drivers/net/i40e/i40e_ethdev.h | 17 +-
> drivers/net/i40e/i40e_ethdev_vf.c | 16 +-
> drivers/net/i40e/i40e_fdir.c | 54 +++---
> drivers/net/i40e/i40e_flow.c | 5 +-
> drivers/net/i40e/i40e_rxtx.c | 57 +++++++
> drivers/net/i40e/i40e_rxtx.h | 1 +
> 7 files changed, 208 insertions(+), 285 deletions(-)
>
> diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
> index 18eac07..e396f73 100644
> --- a/drivers/net/i40e/i40e_ethdev.c
> +++ b/drivers/net/i40e/i40e_ethdev.c
<snip>
>
> static int
> -i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
> +i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg,
> + struct i40e_adapter *adapter)
how about chaning the parameter order?
i40e_hash_global_config_check(struct i40e_adapter *adapter, struct rte_eth_hash_global_conf *g_cfg)?
> {
> uint32_t i;
> - uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
> + uint32_t mask0, i40e_mask = adapter->flow_types_mask;
>
> if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
> g_cfg->hash_func !=
> RTE_ETH_HASH_FUNCTION_SIMPLE_XOR && @@ -7899,64 +7839,32 @@
> static int i40e_set_hash_filter_global_config(struct i40e_hw *hw,
> struct rte_eth_hash_global_conf *g_cfg) {
> + struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
> int ret;
> - uint16_t i;
> + uint16_t i, j;
> uint32_t reg;
> - uint32_t mask0 = g_cfg->valid_bit_mask[0];
> - enum i40e_filter_pctype pctype;
> + /*
> + * We work only with lowest 32 bits which is not correct, but to work
> + * properly the valid_bit_mask size should be increased up to 64 bits
> + * and this will brake ABI. This modification will be done in next
> release
> + */
> + uint32_t mask0 = g_cfg->valid_bit_mask[0] &
> +(uint32_t)adapter->flow_types_mask;
>
> /* Check the input parameters */
> - ret = i40e_hash_global_config_check(g_cfg);
> + ret = i40e_hash_global_config_check(g_cfg, adapter);
> if (ret < 0)
> return ret;
>
> - for (i = 0; mask0 && i < UINT32_BIT; i++) {
> - if (!(mask0 & (1UL << i)))
> - continue;
> - mask0 &= ~(1UL << i);
> - /* if flowtype is invalid, continue */
> - if (!I40E_VALID_FLOW(i))
> - continue;
> - pctype = i40e_flowtype_to_pctype(i);
> - reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
> - I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
> - if (hw->mac.type == I40E_MAC_X722) {
> - if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP)
> {
<snip>
> - reg);
> - } else {
> - i40e_write_rx_ctl(hw,
> I40E_GLQF_HSYM(pctype),
> - reg);
> + for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT32_BIT; i++) {
Should it be like following?
for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT32_BIT; i++) {
> + if (mask0 & (1UL << i)) {
> + reg = (g_cfg->sym_hash_enable_mask[0] & (1UL <<
> i)) ?
> +
> I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
> +
> + for (j = I40E_FILTER_PCTYPE_INVALID + 1;
> + j < I40E_FILTER_PCTYPE_MAX; j++) {
> + if (adapter->pctypes_tbl[i] & (1ULL << j))
> + i40e_write_rx_ctl(hw,
> I40E_GLQF_HSYM(j), reg);
> }
> - } else {
> - i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype),
> reg);
> }
> }
>
> @@ -8581,13 +8489,10 @@ i40e_filter_input_set_init(struct i40e_pf *pf)
>
> for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
> pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
> - if (hw->mac.type == I40E_MAC_X722) {
> - if (!I40E_VALID_PCTYPE_X722(pctype))
> - continue;
> - } else {
> - if (!I40E_VALID_PCTYPE(pctype))
> - continue;
> - }
> + uint16_t flow_type = i40e_pctype_to_flowtype(pf->adapter,
> pctype);
Move the variable to the beginning of the function according to the code style.
> +
> + if (flow_type == RTE_ETH_FLOW_UNKNOWN)
> + continue;
>
> input_set = i40e_get_default_input_set(pctype);
>
> @@ -8650,7 +8555,8 @@ i40e_hash_filter_inset_select(struct i40e_hw *hw,
> return -EINVAL;
> }
>
> - if (!I40E_VALID_FLOW(conf->flow_type)) {
> + pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
> + if (pctype == I40E_FILTER_PCTYPE_INVALID) {
> PMD_DRV_LOG(ERR, "invalid flow_type input.");
> return -EINVAL;
> }
<snip>
> diff --git a/drivers/net/i40e/i40e_fdir.c b/drivers/net/i40e/i40e_fdir.c index
> 84c0a1f..810d384 100644
> --- a/drivers/net/i40e/i40e_fdir.c
> +++ b/drivers/net/i40e/i40e_fdir.c
> @@ -344,15 +344,10 @@ i40e_init_flx_pld(struct i40e_pf *pf)
> /* initialize the masks */
> for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
> pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
> - if (hw->mac.type == I40E_MAC_X722) {
> - if (!I40E_VALID_PCTYPE_X722(
> - (enum i40e_filter_pctype)pctype))
> - continue;
> - } else {
> - if (!I40E_VALID_PCTYPE(
> - (enum i40e_filter_pctype)pctype))
> - continue;
> - }
> + uint16_t flow_type = i40e_pctype_to_flowtype(pf->adapter,
> pctype);
Same comments here, move 'uint16_t flow_type' to the beginning of the function.
> +
> + if (flow_type == RTE_ETH_FLOW_UNKNOWN)
> + continue;
> pf->fdir.flex_mask[pctype].word_mask = 0;
> i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), 0);
> for (i = 0; i < I40E_FDIR_BITMASK_NUM_WORD; i++) { @@ -
> 449,7 +444,8 @@ i40e_check_fdir_flex_payload(const struct
> rte_eth_flex_payload_cfg *flex_cfg)
> * arguments are valid
> */
> static int
> -i40e_check_fdir_flex_conf(const struct rte_eth_fdir_flex_conf *conf)
> +i40e_check_fdir_flex_conf(const struct rte_eth_fdir_flex_conf *conf,
> + const struct i40e_adapter *adapter)
How about i40e_check_fdir_flex_conf(const struct i40e_adapter *adapter , const struct rte_eth_fdir_flex_conf *conf)?
> {
> const struct rte_eth_flex_payload_cfg *flex_cfg;
> const struct rte_eth_fdir_flex_mask *flex_mask; @@ -486,8 +482,11
> @@ i40e_check_fdir_flex_conf(const struct rte_eth_fdir_flex_conf *conf)
> return -EINVAL;
> }
> for (i = 0; i < conf->nb_flexmasks; i++) {
> + enum i40e_filter_pctype pctype;
Move the variable to the beginning of the function.
> +
> flex_mask = &conf->flex_mask[i];
> - if (!I40E_VALID_FLOW(flex_mask->flow_type)) {
> + pctype = i40e_flowtype_to_pctype(adapter, flex_mask-
> >flow_type);
> + if (pctype == I40E_FILTER_PCTYPE_INVALID) {
> PMD_DRV_LOG(WARNING, "invalid flow type.");
> return -EINVAL;
> }
<snip>
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