[dpdk-dev] [PATCH v3 03/12] event/octeontx: add support to create and free timer adapter

[Jerin Jacob]

-----Original Message-----
> Date: Tue,  3 Apr 2018 20:35:05 +0530
> From: Pavan Nikhilesh <pbhagavatula at caviumnetworks.com>
> To: jerin.jacob at caviumnetworks.com, santosh.shukla at caviumnetworks.com,
>  erik.g.carrillo at intel.com
> Cc: dev at dpdk.org, Pavan Nikhilesh <pbhagavatula at caviumnetworks.com>
> Subject: [dpdk-dev] [PATCH v3 03/12] event/octeontx: add support to create
>  and free timer adapter
> X-Mailer: git-send-email 2.16.3
> 
> When the application requests to create a timer device, Octeontx TIM
> create does the following:
> - Get the requested TIMvf ring based on adapter_id.
> - Verify the config parameters supplied.
> - Allocate memory required for
>   * Buckets based on min and max timeout supplied.
>   * Allocate the chunk pool based on the number of timers.
> - Clear the interrupts.
> 
> On Free:
> - Free the allocated bucket and chunk memory.
> - Free private data used by TIMvf.
> 
> Signed-off-by: Pavan Nikhilesh <pbhagavatula at caviumnetworks.com>
> ---
> +static int
> +timvf_ring_create(struct rte_event_timer_adapter *adptr)
> +{
> +
> +	switch (rcfg->clk_src) {
> +	case RTE_EVENT_TIMER_ADAPTER_CPU_CLK:

while defining the enum, equate TIM_CLK_SRC_SCLK, TIM_CLK_SRC_GPIO..
values to RTE_EVENT_TIMER_ADAPTER_CPU_CLK,
RTE_EVENT_TIMER_ADAPTER_EXT_CLK0 ..
etc to avoid switch case.

> +		timr->clk_src = TIM_CLK_SRC_SCLK;
> +		break;
> +	case RTE_EVENT_TIMER_ADAPTER_EXT_CLK0:
> +		timr->clk_src = TIM_CLK_SRC_GPIO;
> +		break;
> +	case RTE_EVENT_TIMER_ADAPTER_EXT_CLK1:
> +		timr->clk_src = TIM_CLK_SRC_GTI;
> +		break;
> +	case RTE_EVENT_TIMER_ADAPTER_EXT_CLK2:
> +		timr->clk_src = TIM_CLK_SRC_PTP;
> +		break;
> +	default:
> +		timvf_log_err("Invalid clk source specified.");
> +		goto cfg_err;
> +	}
> +
> +	timvf_write64(0, (uint8_t *)timr->vbar0 + TIM_VRING_BASE);
> +	timvf_write64(0, (uint8_t *)timr->vbar0 + TIM_VF_NRSPERR_INT);
> +	timvf_write64(0, (uint8_t *)timr->vbar0 + TIM_VF_NRSPERR_INT_W1S);
> +	timvf_write64(0x7, (uint8_t *)timr->vbar0 + TIM_VF_NRSPERR_ENA_W1C);
> +	timvf_write64(0x7, (uint8_t *)timr->vbar0 + TIM_VF_NRSPERR_ENA_W1S);
> +
> +	return 0;
> +mem_err:
> +	rte_free(timr);
> +	return -ENOMEM;
> +cfg_err:
> +	rte_free(timr);
> +	return -EINVAL;
> +}
> +
> +static int
> +timvf_ring_free(struct rte_event_timer_adapter *adptr)
> +{
> +	struct timvf_ring *timr = adptr->data->adapter_priv;
> +	rte_mempool_free(timr->meta.chunk_pool);
> +	rte_free(timr->meta.bkt);
> +	rte_free(adptr->data->adapter_priv);
> +	return 0;
> +}
> +
> +static struct rte_event_timer_adapter_ops timvf_ops = {

use const

> +		.init		= timvf_ring_create,

Found additional tab

> +		.uninit		= timvf_ring_free,
> +		.get_info	= timvf_ring_info_get,
> +};
> +
> +int
> +timvf_timer_adapter_caps_get(const struct rte_eventdev *dev, uint64_t flags,
> +		uint32_t *caps, const struct rte_event_timer_adapter_ops **ops)
> +{
> +	RTE_SET_USED(dev);
> +	RTE_SET_USED(flags);
> +	*caps = RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT;
> +	*ops = &timvf_ops;
> +	return -EINVAL;
> +}
> +enum timvf_clk_src {
> +	TIM_CLK_SRC_SCLK,

See above comment.

> +	TIM_CLK_SRC_GPIO,
> +	TIM_CLK_SRC_GTI,
> +	TIM_CLK_SRC_PTP,
> +};
> +
> +struct timvf_meta {
> +	bkt_id get_target_bkt;
> +	refill_chunk refill_chunk;
> +	struct rte_reciprocal_u64 fast_div;
> +	uint64_t ring_start_cyc;
> +	uint32_t nb_bkts;
> +	struct tim_mem_bucket *bkt;
> +	void *chunk_pool;
> +	uint64_t tck_int;
> +};
> +
> +struct timvf_ring {
> +	struct timvf_meta meta;

IMO, Additional 'meta' indirection can be avoid to reduce the code
clutter.

> +	uint64_t tck_nsec;
> +	void  *vbar0;
> +	void *bkt_pos;
> +	uint64_t max_tout;
> +	uint64_t nb_chunks;
> +	enum timvf_clk_src clk_src;
> +	uint16_t tim_ring_id;
> +} __rte_cache_aligned;
> +