[dpdk-dev] [PATCH 03/28] common/cnxk: add support for getting link information

[Jerin Jacob]

On Tue, Jun 1, 2021 at 3:12 AM Tomasz Duszynski <tduszynski at marvell.com> wrote:
>
> Add support for retrieving link information.
>
> Signed-off-by: Tomasz Duszynski <tduszynski at marvell.com>
> Signed-off-by: Jakub Palider <jpalider at marvell.com>
> ---
> +enum roc_bphy_cgx_eth_link_speed {
> +       ROC_BPHY_CGX_ETH_LINK_SPEED_NONE,
> +       ROC_BPHY_CGX_ETH_LINK_SPEED_10M,
> +       ROC_BPHY_CGX_ETH_LINK_SPEED_100M,
> +       ROC_BPHY_CGX_ETH_LINK_SPEED_1G,
> +       ROC_BPHY_CGX_ETH_LINK_SPEED_2HG,
> +       ROC_BPHY_CGX_ETH_LINK_SPEED_5G,
> +       ROC_BPHY_CGX_ETH_LINK_SPEED_10G,
> +       ROC_BPHY_CGX_ETH_LINK_SPEED_20G,
> +       ROC_BPHY_CGX_ETH_LINK_SPEED_25G,
> +       ROC_BPHY_CGX_ETH_LINK_SPEED_40G,
> +       ROC_BPHY_CGX_ETH_LINK_SPEED_50G,
> +       ROC_BPHY_CGX_ETH_LINK_SPEED_80G,
> +       ROC_BPHY_CGX_ETH_LINK_SPEED_100G,
> +       __MAX_ROC_BPHY_CGX_ETH_LINK_SPEED

Better to change to  __ROC_BPHY_CGX_ETH_LINK_SPEED_MAX

> +};
> +
> +enum roc_bphy_cgx_eth_link_fec {
> +       ROC_BPHY_CGX_ETH_LINK_FEC_NONE,
> +       ROC_BPHY_CGX_ETH_LINK_FEC_BASE_R,
> +       ROC_BPHY_CGX_ETH_LINK_FEC_RS,
> +       __MAX_ROC_BPHY_CGX_ETH_LINK_FEC

Same as above.

> +};
> +
> +enum roc_bphy_cgx_eth_link_mode {
> +       ROC_BPHY_CGX_ETH_LINK_MODE_SGMII_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_1000_BASEX_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_QSGMII_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_10G_C2C_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_10G_C2M_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_10G_KR_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_20G_C2C_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_25G_C2C_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_25G_C2M_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_25G_2_C2C_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_25G_CR_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_25G_KR_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_40G_C2C_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_40G_C2M_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_40G_CR4_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_40G_KR4_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_40GAUI_C2C_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_50G_C2C_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_50G_C2M_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_50G_4_C2C_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_50G_CR_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_50G_KR_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_80GAUI_C2C_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_100G_C2C_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_100G_C2M_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_100G_CR4_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_100G_KR4_BIT,
> +       __MAX_ROC_BPHY_CGX_ETH_LINK_MODE


Same as above.


> +};
> +
> +struct roc_bphy_cgx_link_info {
> +       bool link_up;
> +       bool full_duplex;
> +       enum roc_bphy_cgx_eth_link_speed speed;
> +       bool an;
> +       enum roc_bphy_cgx_eth_link_fec fec;
> +       enum roc_bphy_cgx_eth_link_mode mode;
> +};
> +
>  __roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx);
>  __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx);
>