[PATCH v3 1/8] eal: add initial support for RISC-V architecture

[Stephen Hemminger]

On Fri, 13 May 2022 08:50:34 +0200
Heinrich Schuchardt <heinrich.schuchardt at canonical.com> wrote:

> On 5/10/22 17:48, Stanislaw Kardach wrote:
> > From: Michal Mazurek <maz at semihalf.com>
> > 
> > Add all necessary elements for DPDK to compile and run EAL on SiFive
> > Freedom U740 SoC which is based on SiFive U74-MC (ISA: rv64imafdc)
> > core complex.
> > 
> > This includes:
> > 
> > - EAL library implementation for rv64imafdc ISA.
> > - meson build structure for 'riscv' architecture. RTE_ARCH_RISCV define
> >    is added for architecture identification.
> > - xmm_t structure operation stubs as there is no vector support in the
> >    U74 core.
> > 
> > Compilation was tested on Ubuntu and Arch Linux using riscv64 toolchain.
> > Clang compilation currently not supported due to issues with missing
> > relocation relaxation.
> > 
> > Two rte_rdtsc() schemes are provided: stable low-resolution using rdtime
> > (default) and unstable high-resolution using rdcycle. User can override
> > the scheme by defining RTE_RISCV_RDTSC_USE_HPM=1 during compile time of
> > both DPDK and the application. The reasoning for this is as follows.
> > The RISC-V ISA mandates that clock read by rdtime has to be of constant
> > period and synchronized between all hardware threads within 1 tick
> > (chapter 10.1 in version 20191213 of RISC-V spec).
> > However this clock may not be of high-enough frequency for dataplane
> > uses. I.e. on HiFive Unmatched (FU740) it is 1MHz.
> > There is a high-resolution alternative in form of rdcycle which is
> > clocked at the core clock frequency. The drawbacks are that it may be
> > disabled during sleep (WFI) and its frequency might change due to DVFS.

Choosing at compile time is ok for embedded but is undesireable for DPDK
in a distribution.  It sounds like the low-res is equivalent to hpet
and the unstable is same as x86 TSC. Therefore why not follow that
precedent and do the same thing?