[PATCH 4/4] net/mlx5: define index register for linear tables

[Alexander Kozyrev]

Set MLX5_LINEAR_HASH_TAG_INDEX as a special id for the TAG item:
it holds the index in a linear table for a packet to land to.
This rule index in the table uses upper 16-bits of REG_C_3,
handle this TAG item in the modify_field API for setting the index.

Signed-off-by: Alexander Kozyrev <akozyrev at nvidia.com>
---
 drivers/net/mlx5/mlx5_flow.h    |  3 +++
 drivers/net/mlx5/mlx5_flow_dv.c |  6 ++++--
 drivers/net/mlx5/mlx5_flow_hw.c | 12 ++++++++++--
 drivers/net/mlx5/rte_pmd_mlx5.h |  5 +++++
 4 files changed, 22 insertions(+), 4 deletions(-)

diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h
index c2f9ffd760..cd1938ecfd 100644
--- a/drivers/net/mlx5/mlx5_flow.h
+++ b/drivers/net/mlx5/mlx5_flow.h
@@ -17,6 +17,7 @@
 #include <mlx5_prm.h>
 
 #include "mlx5.h"
+#include "rte_pmd_mlx5.h"
 #include "hws/mlx5dr.h"
 
 /* E-Switch Manager port, used for rte_flow_item_port_id. */
@@ -1588,6 +1589,8 @@ flow_hw_get_reg_id(enum rte_flow_item_type type, uint32_t id)
 	case RTE_FLOW_ITEM_TYPE_METER_COLOR:
 		return mlx5_flow_hw_aso_tag;
 	case RTE_FLOW_ITEM_TYPE_TAG:
+		if (id == MLX5_LINEAR_HASH_TAG_INDEX)
+			return REG_C_3;
 		MLX5_ASSERT(id < MLX5_FLOW_HW_TAGS_MAX);
 		return mlx5_flow_hw_avl_tags[id];
 	default:
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 84fc725738..c6c0eae077 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -1761,6 +1761,8 @@ mlx5_flow_field_id_to_modify_info
 			MLX5_ASSERT(data->offset + width <= 32);
 			int reg;
 
+			off_be = (data->level == MLX5_LINEAR_HASH_TAG_INDEX) ?
+				 16 - (data->offset + width) + 16 : data->offset;
 			if (priv->sh->config.dv_flow_en == 2)
 				reg = flow_hw_get_reg_id(RTE_FLOW_ITEM_TYPE_TAG,
 							 data->level);
@@ -1775,9 +1777,9 @@ mlx5_flow_field_id_to_modify_info
 						reg_to_field[reg]};
 			if (mask)
 				mask[idx] = flow_modify_info_mask_32
-					(width, data->offset);
+					(width, off_be);
 			else
-				info[idx].offset = data->offset;
+				info[idx].offset = off_be;
 		}
 		break;
 	case RTE_FLOW_FIELD_MARK:
diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c
index 6f391d990d..36a7f2a3bd 100644
--- a/drivers/net/mlx5/mlx5_flow_hw.c
+++ b/drivers/net/mlx5/mlx5_flow_hw.c
@@ -1017,7 +1017,11 @@ flow_hw_modify_field_compile(struct rte_eth_dev *dev,
 		    conf->dst.field == RTE_FLOW_FIELD_METER_COLOR ||
 		    conf->dst.field == (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG) {
 			value = *(const unaligned_uint32_t *)item.spec;
-			value = rte_cpu_to_be_32(value);
+			if (conf->dst.field == RTE_FLOW_FIELD_TAG &&
+			    conf->dst.level == MLX5_LINEAR_HASH_TAG_INDEX)
+				value = rte_cpu_to_be_32(value << 16);
+			else
+				value = rte_cpu_to_be_32(value);
 			item.spec = &value;
 		} else if (conf->dst.field == RTE_FLOW_FIELD_GTP_PSC_QFI) {
 			/*
@@ -2046,7 +2050,11 @@ flow_hw_modify_field_construct(struct mlx5_hw_q_job *job,
 	    mhdr_action->dst.field == RTE_FLOW_FIELD_METER_COLOR ||
 	    mhdr_action->dst.field == (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG) {
 		value_p = (unaligned_uint32_t *)values;
-		*value_p = rte_cpu_to_be_32(*value_p);
+		if (mhdr_action->dst.field == RTE_FLOW_FIELD_TAG &&
+		    mhdr_action->dst.level == MLX5_LINEAR_HASH_TAG_INDEX)
+			*value_p = rte_cpu_to_be_32(*value_p << 16);
+		else
+			*value_p = rte_cpu_to_be_32(*value_p);
 	} else if (mhdr_action->dst.field == RTE_FLOW_FIELD_GTP_PSC_QFI) {
 		uint32_t tmp;
 
diff --git a/drivers/net/mlx5/rte_pmd_mlx5.h b/drivers/net/mlx5/rte_pmd_mlx5.h
index b71a291256..5365cd8442 100644
--- a/drivers/net/mlx5/rte_pmd_mlx5.h
+++ b/drivers/net/mlx5/rte_pmd_mlx5.h
@@ -68,6 +68,11 @@ int rte_pmd_mlx5_sync_flow(uint16_t port_id, uint32_t domains);
  */
 #define MLX5_EXTERNAL_RX_QUEUE_ID_MIN (UINT16_MAX - 1000 + 1)
 
+/**
+ * Tag level to set the linear hash index.
+ */
+#define MLX5_LINEAR_HASH_TAG_INDEX 255
+
 /**
  * Update mapping between rte_flow queue index (16 bits) and HW queue index (32
  * bits) for RxQs which is created outside the PMD.
-- 
2.18.2