[dts] [PATCH] tests_ftag: fix expected output time when striping port glort ID

[Lin, Xueqin]

Hi Marvin,

This patch has merged for RubyRapid card, fixed file is rrc.py.
Another patch is new and for BoulderRapid card, file is br.py.

Best regards,
Xueqin
> -----Original Message-----
> From: Liu, Yong
> Sent: Tuesday, August 16, 2016 2:18 PM
> To: xueqin.lin; dts at dpdk.org
> Cc: Lin, Xueqin
> Subject: RE: [dts][PATCH] tests_ftag: fix expected output time when striping
> port glort ID
> 
> Hi Qin, your patch hasn't been merged, so you need to send out patch with all
> the changes.
> 
> > -----Original Message-----
> > From: xueqin.lin [mailto:xlin15 at ecsmtp.sh.intel.com]
> > Sent: Tuesday, August 16, 2016 2:13 PM
> > To: Liu, Yong; dts at dpdk.org
> > Cc: Lin, Xueqin
> > Subject: [dts][PATCH] tests_ftag: fix expected output time when striping
> > port glort ID
> >
> > From: Xueqin Lin <xueqin.lin at intel.com>
> >
> > It is impossible to wait some long time for expected output, just fix as
> > default value.
> >
> >
> > diff --git a/nics/rrc.py b/nics/rrc.py
> > index 62dc8d2..a6ac175 100644
> > --- a/nics/rrc.py
> > +++ b/nics/rrc.py
> > @@ -259,7 +259,7 @@ class RedRockCanyou(NetDevice):
> >              return None
> >          else:
> >              port_value = res.group(2)
> > -        out = self.ctrl_crb.send_expect("show stacking logical-port all",
> > "<0>%",10000)
> > +        out = self.ctrl_crb.send_expect("show stacking logical-port all",
> > "<0>%")
> >          pattern = r"([0-9a-z]{6})+(\s)+(%s)+" %port_value
> >          s = re.compile(pattern)
> >          res = s.search(out)
> > --
> > 2.5.5