[dts] [dts 2/2][PATCH V1] update coremask test case

[xu,huilong]

update list:
1. set log leavel to debug leavel when setup dpdk app
2. skip core 0 when run all core mask.

Signed-off-by: xu,huilong <huilongx.xu at intel.com>
---
 tests/TestSuite_coremask.py | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/tests/TestSuite_coremask.py b/tests/TestSuite_coremask.py
index 4f6f4bd..1fa30e1 100644
--- a/tests/TestSuite_coremask.py
+++ b/tests/TestSuite_coremask.py
@@ -17,7 +17,7 @@ from test_case import TestCase
 # Test class.
 #
 
-command_line = """./%s/app/test -c %s -n %d"""
+command_line = """./%s/app/test -c %s -n %d --log-level 8"""
 
 
 class TestCoremask(TestCase):
@@ -79,11 +79,11 @@ class TestCoremask(TestCase):
 
         out = self.dut.send_expect(command, "RTE>>", 10)
 
-        self.verify("EAL: Master lcore 0 is ready" in out,
-                    "Core 0 not ready")
+        self.verify("EAL: Master lcore 1 is ready" in out,
+                    "Core 1 not ready")
 
-        self.verify("EAL: Detected lcore 0 as core" in out,
-                    "Core 0 not detected")
+        self.verify("EAL: Detected lcore 1 as core" in out,
+                    "Core 1 not detected")
 
         for core in self.all_cores[1:]:
             self.verify("EAL: lcore %s is ready" % core in out,
@@ -99,7 +99,7 @@ class TestCoremask(TestCase):
         Check coremask parsing for more cores than available.
         """
 
-        command_line = """./%s/app/test -c %s -n %d|tee out"""
+        command_line = """./%s/app/test -c %s -n %d --log-level 8|tee out"""
 
         # Default big coremask value 128
         big_coremask_size = 128
-- 
1.9.3