[dts] [PATCH V4] tests/dual_vlan Change the verify outside the loop

[Yao, BingX Y]

Tested-by: yaobing <bingx.y.yao at intel.com>

-----Original Message-----
From: dts [mailto:dts-bounces at dpdk.org] On Behalf Of zhuwenhui
Sent: Saturday, February 2, 2019 9:42 AM
To: dts at dpdk.org
Cc: Zhu, WenhuiX <wenhuix.zhu at intel.com>
Subject: [dts] [PATCH V4] tests/dual_vlan Change the verify outside the loop

Verification should be outside the loop of the query port

Signed-off-by: zhuwenhui <wenhuix.zhu at intel.com>
---
 tests/TestSuite_dual_vlan.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/TestSuite_dual_vlan.py b/tests/TestSuite_dual_vlan.py index d7fba3d..42497ef 100644
--- a/tests/TestSuite_dual_vlan.py
+++ b/tests/TestSuite_dual_vlan.py
@@ -192,7 +192,7 @@ class TestDualVlan(TestCase):
                 time.sleep(1)
                 out = self.dut.send_expect("show port info %s" % port_id, "testpmd> ")
                 port_time_up += 1
-                self.verify("Link status: down" not in out, "Port %s Link down, please check your link" % port_id)
+            self.verify("Link status: down" not in out, "Port %s Link 
+ down, please check your link" % port_id)
 
     def multimode_test(self, caseIndex):
         """
--
2.17.2