[dts] [PATCH V1] add support for cvl

[Peng Zhihong]

add support for cvl

Signed-off-by: Peng Zhihong <zhihongx.peng at intel.com>
---
 tests/TestSuite_userspace_ethtool.py | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/tests/TestSuite_userspace_ethtool.py b/tests/TestSuite_userspace_ethtool.py
index 116fd3a..9a30199 100644
--- a/tests/TestSuite_userspace_ethtool.py
+++ b/tests/TestSuite_userspace_ethtool.py
@@ -546,9 +546,14 @@ class TestUserspaceEthtool(TestCase, IxiaPacketGenerator):
         mtus = [1519, 2048]
         mtu_threshold = 2022
         offset = 0
+
         if self.nic in ['powerville', 'springville']:
             mtu_threshold = 2026
             offset = 4
+        elif self.nic in ['columbiaville_25g', 'columbiaville_100g']:
+            #mtu + ICE_ETH_OVERHEAD  = mtu + HEADER_SIZE['eth'] + offset (ICE_ETH_OVERHEAD is 26)
+            offset = 8
+
         for index in range(len(self.ports)):
             port = self.ports[index]
             # change mtu
@@ -561,12 +566,11 @@ class TestUserspaceEthtool(TestCase, IxiaPacketGenerator):
                 if mtu > mtu_threshold:
                     if self.nic in ['powerville', 'springville']:
                         mtu = mtu_threshold
-                    self.dut.send_expect("stop %s" % index, "EthApp>")
-                    self.dut.send_expect("mtu %d %d" % (index, mtu), "EthApp>")
-                    self.dut.send_expect("open %s" % index, "EthApp>")
+                self.dut.send_expect("stop %s" % index, "EthApp>")
                 self.dut.send_expect("mtu %d %d" % (index, mtu), "EthApp>")
-                time.sleep(5)
+                self.dut.send_expect("open %s" % index, "EthApp>")
                 ori_rx_pkts, _ = self.strip_portstats(index)
+                time.sleep(5)
                 pkt_size = mtu + HEADER_SIZE['eth'] + offset
                 pkt = Packet(pkt_type='UDP', pkt_len=pkt_size)
                 pkt.send_pkt(self.tester, tx_port=intf, count=4)
-- 
2.17.1