[dts] [PATCH V2 3/4] tests/l3fwdacl: modify code to adapt avx512

[Xiang An]

Modify code to adapt rxmod avx512.

Signed-off-by: Xiang An <xiangx.an at intel.com>
---
 tests/TestSuite_l3fwdacl.py | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/tests/TestSuite_l3fwdacl.py b/tests/TestSuite_l3fwdacl.py
index 65c46b0..b812192 100644
--- a/tests/TestSuite_l3fwdacl.py
+++ b/tests/TestSuite_l3fwdacl.py
@@ -40,6 +40,7 @@ import time
 import framework.packet as packet
 import framework.utils as utils
 from framework.test_case import TestCase
+from framework.settings import load_global_setting, DPDK_RXMODE_SETTING
 
 
 class TestL3fwdacl(TestCase):
@@ -638,13 +639,12 @@ class TestL3fwdacl(TestCase):
         cores = self.get_core_list()
         self.verify(cores is not None, "Insufficient cores for speed testing")
 
-        self.eal_para = self.dut.create_eal_parameters(cores=self.get_core_list())
+        self.eal_para = self.dut.create_eal_parameters(cores=self.get_core_list(), other_eal_param='force-max-simd-bitwidth')
         self.core_mask = utils.create_mask(cores)
         print("Core mask: %s" % self.core_mask)
 
         if self.dut.dpdk_version >= '20.11.0':
-            self.eal_para += " --force-max-simd-bitwidth=0"
-
+                self.eal_para += " --force-max-simd-bitwidth=0"
         valid_ports = [port for port in ports if self.tester.get_local_port(port) != -1]
         self.verify(
             len(valid_ports) >= 2, "Insufficient active dut_ports for speed testing")
-- 
1.8.3.1