[dts][PATCH V1]test_plans: add test plan for cvl 1pps

[Tu, Lijuan]

> -----Original Message-----
> From: qifu <qi.fu at intel.com>
> Sent: 2021年12月15日 23:36
> To: dts at dpdk.org
> Cc: Fu, Qi <qi.fu at intel.com>
> Subject: [dts][PATCH V1]test_plans: add test plan for cvl 1pps
> 
> add test plan for dpdk-21.11 new feature, cvl support 1pps.
> 
> Signed-off-by: qifu <qi.fu at intel.com>
> ---
>  test_plans/cvl_1pps_test_plan.rst | 172 ++++++++++++++++++++++++++++++
>  test_plans/index.rst              |   1 +
>  2 files changed, 173 insertions(+)
>  create mode 100644 test_plans/cvl_1pps_test_plan.rst
> 
> diff --git a/test_plans/cvl_1pps_test_plan.rst
> b/test_plans/cvl_1pps_test_plan.rst
> ......
> +Topology
> +--------
> +1node+1nic+2port+fwd
> +2node+1nic+1port+loopback

Sorry, I don't understand the topology.  What does node mean here ?

> ......
> +1. Copy ice OS default package to /lib/firmware/updates/intel/ice/ddp/ice.pkg,
> +   then load driver::
> +
> +    # cp <ice package> /lib/firmware/updates/intel/ice/ddp/ice.pkg
> +    # rmmod ice
> +    # insmod <ice build dir>/ice.ko

Is it necessary to replace the DDP package? "OS default package" seems a very basic package. 

> .......
+    when test the onboard NIC of HCC/SNR platform, the timer = 1, so all the register need to add 4 except GLGEN_GPIO_CTL.

What does  "HCC/SNR " mean ?

Is there any different among pin 0 to pin 3 except the register address.