[dts][PATCH V2]test_plans: add test plan for cvl 1pps

[Tu, Lijuan]

> -----Original Message-----
> From: Qi Fu <qi.fu at intel.com>
> Sent: 2022年1月15日 0:23
> To: dts at dpdk.org
> Cc: Fu, Qi <qi.fu at intel.com>
> Subject: [dts][PATCH V2]test_plans: add test plan for cvl 1pps
> 
> add test plan for cvl 1pps.
> 
> Signed-off-by: Qi Fu <qi.fu at intel.com>
> ---
>  test_plans/cvl_1pps_test_plan.rst | 165 ++++++++++++++++++++++++++++++
>  test_plans/index.rst              |   1 +
>  2 files changed, 166 insertions(+)
>  create mode 100644 test_plans/cvl_1pps_test_plan.rst
>
> +=================
> +CVL PPS Test Plan
> +=================

PPS means packets per second, am I right? If that, "CVL 1PPS signal"  is more reasonable.

> +Topology
> +--------
> +1node+1nic+2port+fwd
> +2node+1nic+1port+loopback

Sorry, I can't understand the topology, could you explain more.

> +    when test the onboard NIC of HCC/SNR platform, the timer = 1, so all the register need to add 4 except GLGEN_GPIO_CTL.

HCC/SNR are not product names, what do they mean?