[dts] [PATCH V1] tests/cvl_pps: add 4 new cases

[Tu, Lijuan]

> -----Original Message-----
> From: Qin Sun <qinx.sun at intel.com>
> Sent: 2021年12月17日 19:08
> To: dts at dpdk.org
> Cc: Fu, Qi <qi.fu at intel.com>; Sun, QinX <qinx.sun at intel.com>
> Subject: [dts] [PATCH V1] tests/cvl_pps: add 4 new cases
> 
> add 4 new cases for pps according to test plan
> 
> Signed-off-by: Qin Sun <qinx.sun at intel.com>

Could you add some description for your core functions: check_register and check_value.

All registers are hard code, so how to compatible to following :

when test the onboard NIC of HCC/SNR platform, the timer = 1, so all the register need to add 4 except GLGEN_GPIO_CTL.

> +# Copyright(c) 2010-2021 Intel Corporation. All rights reserved.

It's the year of 2022, and we don't have copyright of PAST.

> +                self.verify(actual_value != 0,
> +                            'check register failed, expected value is non-zero, actual value is:{}'.format(actual_value))

The verify failure message is valueless, definitely  the actual value is zero, because it is checkout non-zero.

> +            self.logger.info('check register pass')

Also, it is valueless, if target to get stage info, better to use something like: 

Check register <address>: pass

> +    def tear_down(self):
> +        self.dut.kill_all()

Please use "quit()" in testpmd at first, kill_all should be used as a last resort.