[dpdk-stable] patch 'net/i40e: fix parsing QinQ packets type' has been queued to stable release 16.07.1
Yuanhan Liu
yuanhan.liu at linux.intel.com
Wed Oct 12 08:44:24 CEST 2016
Hi,
FYI, your patch has been queued to stable release 16.07.1
Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable
yet. It will be pushed if I get no objections before this Friday.
So please shutout if anyone has objections.
Thanks.
--yliu
---
>From ded8a4e1b43b2cc0b474767c7a3e69e36edb575f Mon Sep 17 00:00:00 2001
From: Beilei Xing <beilei.xing at intel.com>
Date: Mon, 12 Sep 2016 17:41:46 +0800
Subject: [PATCH] net/i40e: fix parsing QinQ packets type
[ upstream commit e536c2e328833dd7a146681ad9a012781573c612 ]
Previously, PTYPE filed in the RX descriptors is not set properly
for QinQ packets. The wrong PTYPE is generated because outer Tag did
not have ORT/PIT configured, so fix this issue by configuring ORT/PIT.
This patch also changes bitmask of outer VLAN tag in L2 header
to support RSS and flow director for QinQ.
Fixes: 4861cde46116 ("i40e: new poll mode driver")
Fixes: 4072d503aaa5 ("i40e: fix VLAN bitmasks for input set")
Signed-off-by: Beilei Xing <beilei.xing at intel.com>
Acked-by: Jingjing Wu <jingjing.wu at intel.com>
---
drivers/net/i40e/i40e_ethdev.c | 27 +++++++++++++++------------
1 file changed, 15 insertions(+), 12 deletions(-)
diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
index 55c4887..be4b530 100644
--- a/drivers/net/i40e/i40e_ethdev.c
+++ b/drivers/net/i40e/i40e_ethdev.c
@@ -202,7 +202,7 @@
/* Source MAC address */
#define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
/* Outer (S-Tag) VLAN tag in the outer L2 header */
-#define I40E_REG_INSET_L2_OUTER_VLAN 0x0200000000000000ULL
+#define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
/* Inner (C-Tag) or single VLAN tag in the outer L2 header */
#define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
/* Single VLAN tag in the inner L2 header */
@@ -724,10 +724,6 @@ static struct rte_driver rte_i40e_driver = {
PMD_REGISTER_DRIVER(rte_i40e_driver, i40e);
DRIVER_REGISTER_PCI_TABLE(i40e, pci_id_i40e_map);
-/*
- * Initialize registers for flexible payload, which should be set by NVM.
- * This should be removed from code once it is fixed in NVM.
- */
#ifndef I40E_GLQF_ORT
#define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
#endif
@@ -735,8 +731,12 @@ DRIVER_REGISTER_PCI_TABLE(i40e, pci_id_i40e_map);
#define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
#endif
-static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
+static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
{
+ /*
+ * Initialize registers for flexible payload, which should be set by NVM.
+ * This should be removed from code once it is fixed in NVM.
+ */
I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
@@ -747,10 +747,12 @@ static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
-
- /* GLQF_PIT Registers */
I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
+
+ /* Initialize registers for parsing packet type of QinQ */
+ I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
+ I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
}
#define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
@@ -1005,11 +1007,12 @@ eth_i40e_dev_init(struct rte_eth_dev *dev)
}
/*
- * To work around the NVM issue,initialize registers
- * for flexible payload by software.
- * It should be removed once issues are fixed in NVM.
+ * To work around the NVM issue, initialize registers
+ * for flexible payload and packet type of QinQ by
+ * software. It should be removed once issues are fixed
+ * in NVM.
*/
- i40e_flex_payload_reg_init(hw);
+ i40e_GLQF_reg_init(hw);
/* Initialize the input set for filters (hash and fd) to default value */
i40e_filter_input_set_init(pf);
--
1.9.0
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