[dpdk-stable] patch 'net/i40e: fix ethertype filter on X722' has been queued to stable release 16.11.1
Yuanhan Liu
yuanhan.liu at linux.intel.com
Wed Feb 15 07:26:31 CET 2017
Hi,
FYI, your patch has been queued to stable release 16.11.1
Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable
yet. It will be pushed if I get no objections before 02/18/17.
So please shout if anyone has objections.
Thanks.
--yliu
---
>From 2ab977942908e2f348c7733b6ca523a54eb756c8 Mon Sep 17 00:00:00 2001
From: Jeff Guo <jia.guo at intel.com>
Date: Tue, 7 Feb 2017 11:52:19 +0800
Subject: [PATCH] net/i40e: fix ethertype filter on X722
[ upstream commit e06bad05dc125f3fd610e3ee09d03c844edc92cf ]
The GL_SWR_PRI_JOIN_MAP registers are effective on filters, changing
the register's default value will fail the ethertype filter.
The GL_SWR_PRI_JOIN_MAP values are different for each NIC, and current
X722 register values are wrong.
Fix X722 ethertype filter by setting registers to X722 default NVM
values.
Fixes: 92fbf2cbdff4 ("i40e: support X722 and its A0 hardware")
Signed-off-by: Jeff Guo <jia.guo at intel.com>
Acked-by: Jingjing Wu <jingjing.wu at intel.com>
---
drivers/net/i40e/i40e_ethdev.c | 27 ++++++++++++++++++++++++---
1 file changed, 24 insertions(+), 3 deletions(-)
diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
index 968956f..b14f18d 100644
--- a/drivers/net/i40e/i40e_ethdev.c
+++ b/drivers/net/i40e/i40e_ethdev.c
@@ -8284,6 +8284,10 @@ i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
#define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
#define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
+/* For X722 */
+#define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
+#define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
+
/* For X710 */
#define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
/* For XL710 */
@@ -8306,7 +8310,6 @@ i40e_dev_sync_phy_type(struct i40e_hw *hw)
return 0;
}
-
static void
i40e_configure_registers(struct i40e_hw *hw)
{
@@ -8314,8 +8317,8 @@ i40e_configure_registers(struct i40e_hw *hw)
uint32_t addr;
uint64_t val;
} reg_table[] = {
- {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
- {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
+ {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
+ {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
{I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
};
uint64_t reg;
@@ -8323,6 +8326,24 @@ i40e_configure_registers(struct i40e_hw *hw)
int ret;
for (i = 0; i < RTE_DIM(reg_table); i++) {
+ if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
+ if (hw->mac.type == I40E_MAC_X722) /* For X722 */
+ reg_table[i].val =
+ I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
+ else /* For X710/XL710/XXV710 */
+ reg_table[i].val =
+ I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE;
+ }
+
+ if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
+ if (hw->mac.type == I40E_MAC_X722) /* For X722 */
+ reg_table[i].val =
+ I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
+ else /* For X710/XL710/XXV710 */
+ reg_table[i].val =
+ I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
+ }
+
if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
--
1.9.0
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