[dpdk-stable] patch 'net/mlx5: optimize Tx doorbell write' has been queued to stable release 18.08.1
Kevin Traynor
ktraynor at redhat.com
Thu Nov 29 14:20:49 CET 2018
Hi,
FYI, your patch has been queued to stable release 18.08.1
Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 12/08/18. So please
shout if anyone has objections.
Also note that after the patch there's a diff of the upstream commit vs the patch applied
to the branch. If the code is different (ie: not only metadata diffs), due for example to
a change in context or macro names, please double check it.
Thanks.
Kevin Traynor
---
>From 25edba0ea0a2262fd8b6efd3fa80b4060ead29f6 Mon Sep 17 00:00:00 2001
From: Yongseok Koh <yskoh at mellanox.com>
Date: Thu, 15 Nov 2018 10:29:19 +0000
Subject: [PATCH] net/mlx5: optimize Tx doorbell write
[ upstream commit 317e64739de05a67406f43dd1860433359a81435 ]
Unnecessary volatile attribute keeps compiler from further optimizing the
code and this results in a little performance drop (~2%). Because of memory
barriers, it is safe to remove.
Fixes: 6bf10ab69be0 ("net/mlx5: support 32-bit systems")
Signed-off-by: Yongseok Koh <yskoh at mellanox.com>
Acked-by: Shahaf Shuler <shahafs at mellanox.com>
---
drivers/net/mlx5/mlx5_rxtx.h | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h
index e1dc6db21..d06e1e795 100644
--- a/drivers/net/mlx5/mlx5_rxtx.h
+++ b/drivers/net/mlx5/mlx5_rxtx.h
@@ -379,15 +379,14 @@ uint32_t mlx5_tx_update_ext_mp(struct mlx5_txq_data *txq, uintptr_t addr,
*/
static __rte_always_inline void
-__mlx5_uar_write64_relaxed(uint64_t val, volatile void *addr,
+__mlx5_uar_write64_relaxed(uint64_t val, void *addr,
rte_spinlock_t *lock __rte_unused)
{
#ifdef RTE_ARCH_64
- rte_write64_relaxed(val, addr);
+ *(uint64_t *)addr = val;
#else /* !RTE_ARCH_64 */
rte_spinlock_lock(lock);
- rte_write32_relaxed(val, addr);
+ *(uint32_t *)addr = val;
rte_io_wmb();
- rte_write32_relaxed(val >> 32,
- (volatile void *)((volatile char *)addr + 4));
+ *((uint32_t *)addr + 1) = val >> 32;
rte_spinlock_unlock(lock);
#endif
@@ -407,5 +406,5 @@ __mlx5_uar_write64_relaxed(uint64_t val, volatile void *addr,
*/
static __rte_always_inline void
-__mlx5_uar_write64(uint64_t val, volatile void *addr, rte_spinlock_t *lock)
+__mlx5_uar_write64(uint64_t val, void *addr, rte_spinlock_t *lock)
{
rte_io_wmb();
--
2.19.0
---
Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- - 2018-11-29 13:11:36.294946977 +0000
+++ 0048-net-mlx5-optimize-Tx-doorbell-write.patch 2018-11-29 13:11:34.000000000 +0000
@@ -1,14 +1,15 @@
-From 317e64739de05a67406f43dd1860433359a81435 Mon Sep 17 00:00:00 2001
+From 25edba0ea0a2262fd8b6efd3fa80b4060ead29f6 Mon Sep 17 00:00:00 2001
From: Yongseok Koh <yskoh at mellanox.com>
Date: Thu, 15 Nov 2018 10:29:19 +0000
Subject: [PATCH] net/mlx5: optimize Tx doorbell write
+[ upstream commit 317e64739de05a67406f43dd1860433359a81435 ]
+
Unnecessary volatile attribute keeps compiler from further optimizing the
code and this results in a little performance drop (~2%). Because of memory
barriers, it is safe to remove.
Fixes: 6bf10ab69be0 ("net/mlx5: support 32-bit systems")
-Cc: stable at dpdk.org
Signed-off-by: Yongseok Koh <yskoh at mellanox.com>
Acked-by: Shahaf Shuler <shahafs at mellanox.com>
@@ -17,10 +18,10 @@
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h
-index 59fb43fef..e210453fe 100644
+index e1dc6db21..d06e1e795 100644
--- a/drivers/net/mlx5/mlx5_rxtx.h
+++ b/drivers/net/mlx5/mlx5_rxtx.h
-@@ -380,15 +380,14 @@ uint32_t mlx5_tx_update_ext_mp(struct mlx5_txq_data *txq, uintptr_t addr,
+@@ -379,15 +379,14 @@ uint32_t mlx5_tx_update_ext_mp(struct mlx5_txq_data *txq, uintptr_t addr,
*/
static __rte_always_inline void
-__mlx5_uar_write64_relaxed(uint64_t val, volatile void *addr,
@@ -40,7 +41,7 @@
+ *((uint32_t *)addr + 1) = val >> 32;
rte_spinlock_unlock(lock);
#endif
-@@ -408,5 +407,5 @@ __mlx5_uar_write64_relaxed(uint64_t val, volatile void *addr,
+@@ -407,5 +406,5 @@ __mlx5_uar_write64_relaxed(uint64_t val, volatile void *addr,
*/
static __rte_always_inline void
-__mlx5_uar_write64(uint64_t val, volatile void *addr, rte_spinlock_t *lock)
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