[dpdk-stable] patch 'net/ixgbe: fix MACsec setting' has been queued to LTS release 18.11.6
Kevin Traynor
ktraynor at redhat.com
Wed Dec 11 22:25:56 CET 2019
Hi,
FYI, your patch has been queued to LTS release 18.11.6
Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 12/17/19. So please
shout if anyone has objections.
Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.
Queued patches are on a temporary branch at:
https://github.com/kevintraynor/dpdk-stable-queue
This queued commit can be viewed at:
https://github.com/kevintraynor/dpdk-stable-queue/commit/7137dc35798febc3ab6738921eab092ca5c4ac0e
Thanks.
Kevin.
---
>From 7137dc35798febc3ab6738921eab092ca5c4ac0e Mon Sep 17 00:00:00 2001
From: Guinan Sun <guinanx.sun at intel.com>
Date: Thu, 31 Oct 2019 11:31:52 +0000
Subject: [PATCH] net/ixgbe: fix MACsec setting
[ upstream commit 50556c88104cbc0096e90f454dc137258be2099f ]
MACsec setting is not valid when port is stopped.
In order to make it valid, the patch changes the setting
to where port is started.
Fixes: 597f9fafe13b ("app/testpmd: convert to new Tx offloads API")
Signed-off-by: Guinan Sun <guinanx.sun at intel.com>
Reviewed-by: Xiaolong Ye <xiaolong.ye at intel.com>
---
drivers/net/ixgbe/ixgbe_ethdev.c | 149 ++++++++++++++++++++++++++++++
drivers/net/ixgbe/ixgbe_ethdev.h | 19 ++++
drivers/net/ixgbe/rte_pmd_ixgbe.c | 125 ++-----------------------
3 files changed, 175 insertions(+), 118 deletions(-)
diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c
index 74de2ff4e..1336236ba 100644
--- a/drivers/net/ixgbe/ixgbe_ethdev.c
+++ b/drivers/net/ixgbe/ixgbe_ethdev.c
@@ -2591,4 +2591,6 @@ ixgbe_dev_start(struct rte_eth_dev *dev)
struct ixgbe_tm_conf *tm_conf =
IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
+ struct ixgbe_macsec_setting *macsec_ctrl =
+ IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
PMD_INIT_FUNC_TRACE();
@@ -2831,4 +2833,7 @@ skip_link_setup:
ixgbe_dev_link_update(dev, 0);
+ /* setup the macsec ctrl register */
+ ixgbe_dev_macsec_register_enable(dev, macsec_ctrl);
+
return 0;
@@ -2859,4 +2864,7 @@ ixgbe_dev_stop(struct rte_eth_dev *dev)
PMD_INIT_FUNC_TRACE();
+ /* disable mecsec register */
+ ixgbe_dev_macsec_register_disable(dev);
+
rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
@@ -8679,4 +8687,145 @@ ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
}
+void
+ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev,
+ struct ixgbe_macsec_setting *macsec_setting)
+{
+ struct ixgbe_macsec_setting *macsec =
+ IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
+
+ macsec->encrypt_en = macsec_setting->encrypt_en;
+ macsec->replayprotect_en = macsec_setting->replayprotect_en;
+}
+
+void
+ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev)
+{
+ struct ixgbe_macsec_setting *macsec =
+ IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
+
+ macsec->encrypt_en = 0;
+ macsec->replayprotect_en = 0;
+}
+
+void
+ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev,
+ struct ixgbe_macsec_setting *macsec_setting)
+{
+ struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ uint32_t ctrl;
+ uint8_t en = macsec_setting->encrypt_en;
+ uint8_t rp = macsec_setting->replayprotect_en;
+
+ /**
+ * Workaround:
+ * As no ixgbe_disable_sec_rx_path equivalent is
+ * implemented for tx in the base code, and we are
+ * not allowed to modify the base code in DPDK, so
+ * just call the hand-written one directly for now.
+ * The hardware support has been checked by
+ * ixgbe_disable_sec_rx_path().
+ */
+ ixgbe_disable_sec_tx_path_generic(hw);
+
+ /* Enable Ethernet CRC (required by MACsec offload) */
+ ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
+ ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
+ IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
+
+ /* Enable the TX and RX crypto engines */
+ ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
+ ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
+ IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
+
+ ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
+ ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
+ IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
+
+ ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
+ ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
+ ctrl |= 0x3;
+ IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
+
+ /* Enable SA lookup */
+ ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
+ ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
+ ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
+ IXGBE_LSECTXCTRL_AUTH;
+ ctrl |= IXGBE_LSECTXCTRL_AISCI;
+ ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
+ ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
+ IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
+
+ ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
+ ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
+ ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
+ ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
+ if (rp)
+ ctrl |= IXGBE_LSECRXCTRL_RP;
+ else
+ ctrl &= ~IXGBE_LSECRXCTRL_RP;
+ IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
+
+ /* Start the data paths */
+ ixgbe_enable_sec_rx_path(hw);
+ /**
+ * Workaround:
+ * As no ixgbe_enable_sec_rx_path equivalent is
+ * implemented for tx in the base code, and we are
+ * not allowed to modify the base code in DPDK, so
+ * just call the hand-written one directly for now.
+ */
+ ixgbe_enable_sec_tx_path_generic(hw);
+}
+
+void
+ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev)
+{
+ struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ uint32_t ctrl;
+
+ /**
+ * Workaround:
+ * As no ixgbe_disable_sec_rx_path equivalent is
+ * implemented for tx in the base code, and we are
+ * not allowed to modify the base code in DPDK, so
+ * just call the hand-written one directly for now.
+ * The hardware support has been checked by
+ * ixgbe_disable_sec_rx_path().
+ */
+ ixgbe_disable_sec_tx_path_generic(hw);
+
+ /* Disable the TX and RX crypto engines */
+ ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
+ ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
+ IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
+
+ ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
+ ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
+ IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
+
+ /* Disable SA lookup */
+ ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
+ ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
+ ctrl |= IXGBE_LSECTXCTRL_DISABLE;
+ IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
+
+ ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
+ ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
+ ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
+ IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
+
+ /* Start the data paths */
+ ixgbe_enable_sec_rx_path(hw);
+ /**
+ * Workaround:
+ * As no ixgbe_enable_sec_rx_path equivalent is
+ * implemented for tx in the base code, and we are
+ * not allowed to modify the base code in DPDK, so
+ * just call the hand-written one directly for now.
+ */
+ ixgbe_enable_sec_tx_path_generic(hw);
+}
+
RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
diff --git a/drivers/net/ixgbe/ixgbe_ethdev.h b/drivers/net/ixgbe/ixgbe_ethdev.h
index 5023fa13f..418adfa3d 100644
--- a/drivers/net/ixgbe/ixgbe_ethdev.h
+++ b/drivers/net/ixgbe/ixgbe_ethdev.h
@@ -361,4 +361,9 @@ struct rte_flow {
};
+struct ixgbe_macsec_setting {
+ uint8_t encrypt_en;
+ uint8_t replayprotect_en;
+};
+
/*
* Statistics counters collected by the MACsec
@@ -467,4 +472,5 @@ struct ixgbe_adapter {
struct ixgbe_hw_stats stats;
struct ixgbe_macsec_stats macsec_stats;
+ struct ixgbe_macsec_setting macsec_setting;
struct ixgbe_hw_fdir_info fdir;
struct ixgbe_interrupt intr;
@@ -519,4 +525,7 @@ int ixgbe_vf_representor_uninit(struct rte_eth_dev *ethdev);
(&((struct ixgbe_adapter *)adapter)->macsec_stats)
+#define IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(adapter) \
+ (&((struct ixgbe_adapter *)adapter)->macsec_setting)
+
#define IXGBE_DEV_PRIVATE_TO_INTR(adapter) \
(&((struct ixgbe_adapter *)adapter)->intr)
@@ -737,4 +746,14 @@ int ixgbe_config_rss_filter(struct rte_eth_dev *dev,
struct ixgbe_rte_flow_rss_conf *conf, bool add);
+void ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev,
+ struct ixgbe_macsec_setting *macsec_setting);
+
+void ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev);
+
+void ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev,
+ struct ixgbe_macsec_setting *macsec_setting);
+
+void ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev);
+
static inline int
ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
diff --git a/drivers/net/ixgbe/rte_pmd_ixgbe.c b/drivers/net/ixgbe/rte_pmd_ixgbe.c
index 3a874f9a9..49d538ef1 100644
--- a/drivers/net/ixgbe/rte_pmd_ixgbe.c
+++ b/drivers/net/ixgbe/rte_pmd_ixgbe.c
@@ -515,7 +515,6 @@ int
rte_pmd_ixgbe_macsec_enable(uint16_t port, uint8_t en, uint8_t rp)
{
- struct ixgbe_hw *hw;
struct rte_eth_dev *dev;
- uint32_t ctrl;
+ struct ixgbe_macsec_setting macsec_setting;
RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
@@ -523,72 +522,10 @@ rte_pmd_ixgbe_macsec_enable(uint16_t port, uint8_t en, uint8_t rp)
dev = &rte_eth_devices[port];
- if (!is_ixgbe_supported(dev))
- return -ENOTSUP;
+ macsec_setting.encrypt_en = en;
+ macsec_setting.replayprotect_en = rp;
- hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ ixgbe_dev_macsec_setting_save(dev, &macsec_setting);
- /* Stop the data paths */
- if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
- return -ENOTSUP;
- /**
- * Workaround:
- * As no ixgbe_disable_sec_rx_path equivalent is
- * implemented for tx in the base code, and we are
- * not allowed to modify the base code in DPDK, so
- * just call the hand-written one directly for now.
- * The hardware support has been checked by
- * ixgbe_disable_sec_rx_path().
- */
- ixgbe_disable_sec_tx_path_generic(hw);
-
- /* Enable Ethernet CRC (required by MACsec offload) */
- ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
- ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
- IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
-
- /* Enable the TX and RX crypto engines */
- ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
- ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
- IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
-
- ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
- ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
- IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
-
- ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
- ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
- ctrl |= 0x3;
- IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
-
- /* Enable SA lookup */
- ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
- ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
- ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
- IXGBE_LSECTXCTRL_AUTH;
- ctrl |= IXGBE_LSECTXCTRL_AISCI;
- ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
- ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
- IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
-
- ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
- ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
- ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
- ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
- if (rp)
- ctrl |= IXGBE_LSECRXCTRL_RP;
- else
- ctrl &= ~IXGBE_LSECRXCTRL_RP;
- IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
-
- /* Start the data paths */
- ixgbe_enable_sec_rx_path(hw);
- /**
- * Workaround:
- * As no ixgbe_enable_sec_rx_path equivalent is
- * implemented for tx in the base code, and we are
- * not allowed to modify the base code in DPDK, so
- * just call the hand-written one directly for now.
- */
- ixgbe_enable_sec_tx_path_generic(hw);
+ ixgbe_dev_macsec_register_enable(dev, &macsec_setting);
return 0;
@@ -598,7 +535,5 @@ int
rte_pmd_ixgbe_macsec_disable(uint16_t port)
{
- struct ixgbe_hw *hw;
struct rte_eth_dev *dev;
- uint32_t ctrl;
RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
@@ -606,53 +541,7 @@ rte_pmd_ixgbe_macsec_disable(uint16_t port)
dev = &rte_eth_devices[port];
- if (!is_ixgbe_supported(dev))
- return -ENOTSUP;
+ ixgbe_dev_macsec_setting_reset(dev);
- hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
-
- /* Stop the data paths */
- if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
- return -ENOTSUP;
- /**
- * Workaround:
- * As no ixgbe_disable_sec_rx_path equivalent is
- * implemented for tx in the base code, and we are
- * not allowed to modify the base code in DPDK, so
- * just call the hand-written one directly for now.
- * The hardware support has been checked by
- * ixgbe_disable_sec_rx_path().
- */
- ixgbe_disable_sec_tx_path_generic(hw);
-
- /* Disable the TX and RX crypto engines */
- ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
- ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
- IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
-
- ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
- ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
- IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
-
- /* Disable SA lookup */
- ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
- ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
- ctrl |= IXGBE_LSECTXCTRL_DISABLE;
- IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
-
- ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
- ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
- ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
- IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
-
- /* Start the data paths */
- ixgbe_enable_sec_rx_path(hw);
- /**
- * Workaround:
- * As no ixgbe_enable_sec_rx_path equivalent is
- * implemented for tx in the base code, and we are
- * not allowed to modify the base code in DPDK, so
- * just call the hand-written one directly for now.
- */
- ixgbe_enable_sec_tx_path_generic(hw);
+ ixgbe_dev_macsec_register_disable(dev);
return 0;
--
2.21.0
---
Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- - 2019-12-11 21:24:13.077637869 +0000
+++ 0004-net-ixgbe-fix-MACsec-setting.patch 2019-12-11 21:24:12.552653594 +0000
@@ -1 +1 @@
-From 50556c88104cbc0096e90f454dc137258be2099f Mon Sep 17 00:00:00 2001
+From 7137dc35798febc3ab6738921eab092ca5c4ac0e Mon Sep 17 00:00:00 2001
@@ -5,0 +6,2 @@
+[ upstream commit 50556c88104cbc0096e90f454dc137258be2099f ]
+
@@ -11 +12,0 @@
-Cc: stable at dpdk.org
@@ -22 +23 @@
-index 3c7624f3a..06414d110 100644
+index 74de2ff4e..1336236ba 100644
@@ -25 +26 @@
-@@ -2543,4 +2543,6 @@ ixgbe_dev_start(struct rte_eth_dev *dev)
+@@ -2591,4 +2591,6 @@ ixgbe_dev_start(struct rte_eth_dev *dev)
@@ -32 +33 @@
-@@ -2795,4 +2797,7 @@ skip_link_setup:
+@@ -2831,4 +2833,7 @@ skip_link_setup:
@@ -40 +41 @@
-@@ -2826,4 +2831,7 @@ ixgbe_dev_stop(struct rte_eth_dev *dev)
+@@ -2859,4 +2864,7 @@ ixgbe_dev_stop(struct rte_eth_dev *dev)
@@ -48 +49 @@
-@@ -8817,4 +8825,145 @@ ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
+@@ -8679,4 +8687,145 @@ ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
@@ -195 +196 @@
-index 6e9ed2e10..5da6923a1 100644
+index 5023fa13f..418adfa3d 100644
@@ -198 +199 @@
-@@ -366,4 +366,9 @@ struct rte_flow {
+@@ -361,4 +361,9 @@ struct rte_flow {
@@ -208 +209 @@
-@@ -472,4 +477,5 @@ struct ixgbe_adapter {
+@@ -467,4 +472,5 @@ struct ixgbe_adapter {
@@ -214 +215 @@
-@@ -524,4 +530,7 @@ int ixgbe_vf_representor_uninit(struct rte_eth_dev *ethdev);
+@@ -519,4 +525,7 @@ int ixgbe_vf_representor_uninit(struct rte_eth_dev *ethdev);
@@ -222 +223 @@
-@@ -742,4 +751,14 @@ int ixgbe_config_rss_filter(struct rte_eth_dev *dev,
+@@ -737,4 +746,14 @@ int ixgbe_config_rss_filter(struct rte_eth_dev *dev,
@@ -238 +239 @@
-index 9514f2cf5..073fe1e23 100644
+index 3a874f9a9..49d538ef1 100644
@@ -241 +242 @@
-@@ -516,7 +516,6 @@ int
+@@ -515,7 +515,6 @@ int
@@ -250 +251 @@
-@@ -524,72 +523,10 @@ rte_pmd_ixgbe_macsec_enable(uint16_t port, uint8_t en, uint8_t rp)
+@@ -523,72 +522,10 @@ rte_pmd_ixgbe_macsec_enable(uint16_t port, uint8_t en, uint8_t rp)
@@ -327 +328 @@
-@@ -599,7 +536,5 @@ int
+@@ -598,7 +535,5 @@ int
@@ -335 +336 @@
-@@ -607,53 +542,7 @@ rte_pmd_ixgbe_macsec_disable(uint16_t port)
+@@ -606,53 +541,7 @@ rte_pmd_ixgbe_macsec_disable(uint16_t port)
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