[dpdk-stable] patch 'net/mlx5: fix Rx packet padding' has been queued to LTS release 18.11.1

[Kevin Traynor]

Hi,

FYI, your patch has been queued to LTS release 18.11.1

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 02/14/19. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Thanks.

Kevin Traynor

---
>From e7a7c98c8a710f7d1f614d7635ec1cbc29e61613 Mon Sep 17 00:00:00 2001
From: Yongseok Koh <yskoh at mellanox.com>
Date: Tue, 15 Jan 2019 09:38:58 -0800
Subject: [PATCH] net/mlx5: fix Rx packet padding

[ upstream commit 78c7a16daad1b3948b84399203cf225aa153a45c ]

Rx packet padding is supposed to be set by an environment variable -
MLX5_PMD_ENABLE_PADDING, but it has been missing for some time by mistake.
Rather than using such a variable, a PMD parameter (rxq_pkt_pad_en) is
added instead.

Fixes: a1366b1a2be3 ("net/mlx5: add reference counter on DPDK Rx queues")

Signed-off-by: Yongseok Koh <yskoh at mellanox.com>
Reviewed-by: Erez Ferber <erezf at mellanox.com>
Acked-by: Shahaf Shuler <shahafs at mellanox.com>
---
 doc/guides/nics/mlx5.rst | 27 +++++++++++++--------------
 drivers/net/mlx5/mlx5.c  | 18 +++++++++++++++---
 2 files changed, 28 insertions(+), 17 deletions(-)

diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index 23f0f5700..436898acd 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -228,18 +228,4 @@ Environment variables
   since ``LD_LIBRARY_PATH`` has no effect in this case.
 
-- ``MLX5_PMD_ENABLE_PADDING``
-
-  Enables HW packet padding in PCI bus transactions.
-
-  When packet size is cache aligned and CRC stripping is enabled, 4 fewer
-  bytes are written to the PCI bus. Enabling padding makes such packets
-  aligned again.
-
-  In cases where PCI bandwidth is the bottleneck, padding can improve
-  performance by 10%.
-
-  This is disabled by default since this can also decrease performance for
-  unaligned packet sizes.
-
 - ``MLX5_SHUT_UP_BF``
 
@@ -296,4 +282,17 @@ Run-time configuration
   - CPU having 128B cacheline with ConnectX-5 and Bluefield.
 
+- ``rxq_pkt_pad_en`` parameter [int]
+
+  A nonzero value enables padding Rx packet to the size of cacheline on PCI
+  transaction. This feature would waste PCI bandwidth but could improve
+  performance by avoiding partial cacheline write which may cause costly
+  read-modify-copy in memory transaction on some architectures. Disabled by
+  default.
+
+  Supported on:
+
+  - x86_64 with ConnectX-4, ConnectX-4 LX, ConnectX-5, ConnectX-6 and Bluefield.
+  - POWER8 and ARMv8 with ConnectX-4 LX, ConnectX-5, ConnectX-6 and Bluefield.
+
 - ``mprq_en`` parameter [int]
 
diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c
index 9e5cab169..50a62b400 100644
--- a/drivers/net/mlx5/mlx5.c
+++ b/drivers/net/mlx5/mlx5.c
@@ -55,4 +55,7 @@
 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
 
+/* Device parameter to enable padding Rx packet to cacheline size. */
+#define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
+
 /* Device parameter to enable Multi-Packet Rx queue. */
 #define MLX5_RX_MPRQ_EN "mprq_en"
@@ -487,4 +490,6 @@ mlx5_args_check(const char *key, const char *val, void *opaque)
 	} else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
 		config->cqe_pad = !!tmp;
+	} else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
+		config->hw_padding = !!tmp;
 	} else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
 		config->mprq.enabled = !!tmp;
@@ -542,4 +547,5 @@ mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
 		MLX5_RXQ_CQE_COMP_EN,
 		MLX5_RXQ_CQE_PAD_EN,
+		MLX5_RXQ_PKT_PAD_EN,
 		MLX5_RX_MPRQ_EN,
 		MLX5_RX_MPRQ_LOG_STRIDE_NUM,
@@ -736,4 +742,5 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
 	struct priv *priv = NULL;
 	int err = 0;
+	unsigned int hw_padding = 0;
 	unsigned int mps;
 	unsigned int cqe_comp;
@@ -1055,8 +1062,12 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
 		(config.hw_fcs_strip ? "" : "not "));
 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING
-	config.hw_padding = !!attr.rx_pad_end_addr_align;
+	hw_padding = !!attr.rx_pad_end_addr_align;
 #endif
-	DRV_LOG(DEBUG, "hardware Rx end alignment padding is %ssupported",
-		(config.hw_padding ? "" : "not "));
+	if (config.hw_padding && !hw_padding) {
+		DRV_LOG(DEBUG, "Rx end alignment padding isn't supported");
+		config.hw_padding = 0;
+	} else if (config.hw_padding) {
+		DRV_LOG(DEBUG, "Rx end alignment padding is enabled");
+	}
 	config.tso = (attr.tso_caps.max_tso > 0 &&
 		      (attr.tso_caps.supported_qpts &
@@ -1435,4 +1446,5 @@ mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 	/* Default configuration. */
 	dev_config = (struct mlx5_dev_config){
+		.hw_padding = 0,
 		.mps = MLX5_ARG_UNSET,
 		.tx_vec_en = 1,
-- 
2.19.0

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2019-02-07 13:19:56.096046764 +0000
+++ 0024-net-mlx5-fix-Rx-packet-padding.patch	2019-02-07 13:19:55.000000000 +0000
@@ -1,15 +1,16 @@
-From 78c7a16daad1b3948b84399203cf225aa153a45c Mon Sep 17 00:00:00 2001
+From e7a7c98c8a710f7d1f614d7635ec1cbc29e61613 Mon Sep 17 00:00:00 2001
 From: Yongseok Koh <yskoh at mellanox.com>
 Date: Tue, 15 Jan 2019 09:38:58 -0800
 Subject: [PATCH] net/mlx5: fix Rx packet padding
 
+[ upstream commit 78c7a16daad1b3948b84399203cf225aa153a45c ]
+
 Rx packet padding is supposed to be set by an environment variable -
 MLX5_PMD_ENABLE_PADDING, but it has been missing for some time by mistake.
 Rather than using such a variable, a PMD parameter (rxq_pkt_pad_en) is
 added instead.
 
 Fixes: a1366b1a2be3 ("net/mlx5: add reference counter on DPDK Rx queues")
-Cc: stable at dpdk.org
 
 Signed-off-by: Yongseok Koh <yskoh at mellanox.com>
 Reviewed-by: Erez Ferber <erezf at mellanox.com>
@@ -20,10 +21,10 @@
  2 files changed, 28 insertions(+), 17 deletions(-)
 
 diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
-index 5ddca44ee..3f168b161 100644
+index 23f0f5700..436898acd 100644
 --- a/doc/guides/nics/mlx5.rst
 +++ b/doc/guides/nics/mlx5.rst
-@@ -234,18 +234,4 @@ Environment variables
+@@ -228,18 +228,4 @@ Environment variables
    since ``LD_LIBRARY_PATH`` has no effect in this case.
  
 -- ``MLX5_PMD_ENABLE_PADDING``
@@ -42,7 +43,7 @@
 -
  - ``MLX5_SHUT_UP_BF``
  
-@@ -302,4 +288,17 @@ Run-time configuration
+@@ -296,4 +282,17 @@ Run-time configuration
    - CPU having 128B cacheline with ConnectX-5 and Bluefield.
  
 +- ``rxq_pkt_pad_en`` parameter [int]
@@ -61,7 +62,7 @@
  - ``mprq_en`` parameter [int]
  
 diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c
-index a84e1afa0..741bc7fc0 100644
+index 9e5cab169..50a62b400 100644
 --- a/drivers/net/mlx5/mlx5.c
 +++ b/drivers/net/mlx5/mlx5.c
 @@ -55,4 +55,7 @@
@@ -91,7 +92,7 @@
 +	unsigned int hw_padding = 0;
  	unsigned int mps;
  	unsigned int cqe_comp;
-@@ -1061,8 +1068,12 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
+@@ -1055,8 +1062,12 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
  		(config.hw_fcs_strip ? "" : "not "));
  #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING
 -	config.hw_padding = !!attr.rx_pad_end_addr_align;
@@ -107,7 +108,7 @@
 +	}
  	config.tso = (attr.tso_caps.max_tso > 0 &&
  		      (attr.tso_caps.supported_qpts &
-@@ -1441,4 +1452,5 @@ mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
+@@ -1435,4 +1446,5 @@ mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
  	/* Default configuration. */
  	dev_config = (struct mlx5_dev_config){
 +		.hw_padding = 0,