[dpdk-stable] [PATCH] net/mlx5: fix match on Ethertype

[Dekel Peled]

HW supports match on one Ethertype, the Ethertype following the last
VLAN tag of the packet (see PRM).
Previous patch added specific handling for packets with VLAN tag,
after setting match on Ethertype.

This patch moves the handling of packets with VLAN tag, to be done
before and instead of setting match on Ethertype.

Fixes: 00f75a40576b ("net/mlx5: fix VLAN match for DV mode")
Cc: stable at dpdk.org

Signed-off-by: Dekel Peled <dekelp at mellanox.com>
Acked-by: Matan Azrad <matan at mellanox.com>

---
 drivers/net/mlx5/mlx5_flow_dv.c | 18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 467d1ce..764f3b2 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -5213,19 +5213,27 @@ struct field_modify_info modify_tcp[] = {
 	/* The value must be in the range of the mask. */
 	for (i = 0; i < sizeof(eth_m->dst); ++i)
 		l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
-	MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
-		 rte_be_to_cpu_16(eth_m->type));
-	l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
-	*(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
 	if (eth_v->type) {
 		/* When ethertype is present set mask for tagged VLAN. */
 		MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
 		/* Set value for tagged VLAN if ethertype is 802.1Q. */
 		if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
-		    eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ))
+		    eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
 			MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
 				 1);
+			/* Return here to avoid setting match on ethertype. */
+			return;
+		}
 	}
+	/*
+	 * HW supports match on one Ethertype, the Ethertype following the last
+	 * VLAN tag of the packet (see PRM).
+	 * Set match on ethertype only if ETH header is not followed by VLAN.
+	 */
+	MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
+		 rte_be_to_cpu_16(eth_m->type));
+	l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
+	*(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
 }
 
 /**
-- 
1.8.3.1