[dpdk-stable] patch 'eal/armv8: fix timer frequency calibration with PMU' has been queued to stable release 19.11.4

[luca.boccassi at gmail.com]

Hi,

FYI, your patch has been queued to stable release 19.11.4

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 07/26/20. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Thanks.

Luca Boccassi

---
>From 9fd723070318d14eef5b7b5c535a29956e861e36 Mon Sep 17 00:00:00 2001
From: Honnappa Nagarahalli <honnappa.nagarahalli at arm.com>
Date: Fri, 26 Jun 2020 15:35:01 -0500
Subject: [PATCH] eal/armv8: fix timer frequency calibration with PMU

[ upstream commit 97c910139baf007b729388b0c3c24b894e4b6d3e ]

get_tsc_freq uses 'nanosleep' system call to calculate the CPU
frequency. However, 'nanosleep' results in the process getting
un-scheduled. The kernel saves and restores the PMU state. This
ensures that the PMU cycles are not counted towards a sleeping
process. When RTE_ARM_EAL_RDTSC_USE_PMU is defined, this results
in incorrect CPU frequency calculation. This logic is replaced
with generic counter based loop.

Bugzilla ID: 450
Fixes: f91bcbb2d9a6 ("eal/armv8: use high-resolution cycle counter")

Signed-off-by: Honnappa Nagarahalli <honnappa.nagarahalli at arm.com>
Reviewed-by: Ruifeng Wang <ruifeng.wang at arm.com>
Reviewed-by: Dharmik Thakkar <dharmik.thakkar at arm.com>
Reviewed-by: Phil Yang <phil.yang at arm.com>
Acked-by: Jerin Jacob <jerinj at marvell.com>
---
 lib/librte_eal/common/arch/arm/rte_cycles.c   | 27 +++++++++--
 .../common/include/arch/arm/rte_cycles_64.h   | 45 ++++++++++++++++---
 2 files changed, 63 insertions(+), 9 deletions(-)

diff --git a/lib/librte_eal/common/arch/arm/rte_cycles.c b/lib/librte_eal/common/arch/arm/rte_cycles.c
index 3500d523e..5bd29b24b 100644
--- a/lib/librte_eal/common/arch/arm/rte_cycles.c
+++ b/lib/librte_eal/common/arch/arm/rte_cycles.c
@@ -3,14 +3,35 @@
  */
 
 #include "eal_private.h"
+#include "rte_cycles.h"
 
 uint64_t
 get_tsc_freq_arch(void)
 {
 #if defined RTE_ARCH_ARM64 && !defined RTE_ARM_EAL_RDTSC_USE_PMU
-	uint64_t freq;
-	asm volatile("mrs %0, cntfrq_el0" : "=r" (freq));
-	return freq;
+	return __rte_arm64_cntfrq();
+#elif defined RTE_ARCH_ARM64 && defined RTE_ARM_EAL_RDTSC_USE_PMU
+#define CYC_PER_1MHZ 1E6
+	/* Use the generic counter ticks to calculate the PMU
+	 * cycle frequency.
+	 */
+	uint64_t ticks;
+	uint64_t start_ticks, cur_ticks;
+	uint64_t start_pmu_cycles, end_pmu_cycles;
+
+	/* Number of ticks for 1/10 second */
+	ticks = __rte_arm64_cntfrq() / 10;
+
+	start_ticks = __rte_arm64_cntvct_precise();
+	start_pmu_cycles = rte_rdtsc_precise();
+	do {
+		cur_ticks = __rte_arm64_cntvct();
+	} while ((cur_ticks - start_ticks) < ticks);
+	end_pmu_cycles = rte_rdtsc_precise();
+
+	/* Adjust the cycles to next 1Mhz */
+	return RTE_ALIGN_MUL_CEIL(end_pmu_cycles - start_pmu_cycles,
+			CYC_PER_1MHZ) * 10;
 #else
 	return 0;
 #endif
diff --git a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h
index da557b6a1..e41f9dbd6 100644
--- a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h
+++ b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: BSD-3-Clause
  * Copyright(c) 2015 Cavium, Inc
+ * Copyright(c) 2020 Arm Limited
  */
 
 #ifndef _RTE_CYCLES_ARM64_H_
@@ -11,6 +12,33 @@ extern "C" {
 
 #include "generic/rte_cycles.h"
 
+/** Read generic counter frequency */
+static __rte_always_inline uint64_t
+__rte_arm64_cntfrq(void)
+{
+	uint64_t freq;
+
+	asm volatile("mrs %0, cntfrq_el0" : "=r" (freq));
+	return freq;
+}
+
+/** Read generic counter */
+static __rte_always_inline uint64_t
+__rte_arm64_cntvct(void)
+{
+	uint64_t tsc;
+
+	asm volatile("mrs %0, cntvct_el0" : "=r" (tsc));
+	return tsc;
+}
+
+static __rte_always_inline uint64_t
+__rte_arm64_cntvct_precise(void)
+{
+	asm volatile("isb" : : : "memory");
+	return __rte_arm64_cntvct();
+}
+
 /**
  * Read the time base register.
  *
@@ -25,10 +53,7 @@ extern "C" {
 static inline uint64_t
 rte_rdtsc(void)
 {
-	uint64_t tsc;
-
-	asm volatile("mrs %0, cntvct_el0" : "=r" (tsc));
-	return tsc;
+	return __rte_arm64_cntvct();
 }
 #else
 /**
@@ -49,14 +74,22 @@ rte_rdtsc(void)
  * asm volatile("msr pmcr_el0, %0" : : "r" (val));
  *
  */
-static inline uint64_t
-rte_rdtsc(void)
+
+/** Read PMU cycle counter */
+static __rte_always_inline uint64_t
+__rte_arm64_pmccntr(void)
 {
 	uint64_t tsc;
 
 	asm volatile("mrs %0, pmccntr_el0" : "=r"(tsc));
 	return tsc;
 }
+
+static inline uint64_t
+rte_rdtsc(void)
+{
+	return __rte_arm64_pmccntr();
+}
 #endif
 
 static inline uint64_t
-- 
2.20.1

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2020-07-24 12:53:51.688834869 +0100
+++ 0081-eal-armv8-fix-timer-frequency-calibration-with-PMU.patch	2020-07-24 12:53:48.307006832 +0100
@@ -1,8 +1,10 @@
-From 97c910139baf007b729388b0c3c24b894e4b6d3e Mon Sep 17 00:00:00 2001
+From 9fd723070318d14eef5b7b5c535a29956e861e36 Mon Sep 17 00:00:00 2001
 From: Honnappa Nagarahalli <honnappa.nagarahalli at arm.com>
 Date: Fri, 26 Jun 2020 15:35:01 -0500
 Subject: [PATCH] eal/armv8: fix timer frequency calibration with PMU
 
+[ upstream commit 97c910139baf007b729388b0c3c24b894e4b6d3e ]
+
 get_tsc_freq uses 'nanosleep' system call to calculate the CPU
 frequency. However, 'nanosleep' results in the process getting
 un-scheduled. The kernel saves and restores the PMU state. This
@@ -13,7 +15,6 @@
 
 Bugzilla ID: 450
 Fixes: f91bcbb2d9a6 ("eal/armv8: use high-resolution cycle counter")
-Cc: stable at dpdk.org
 
 Signed-off-by: Honnappa Nagarahalli <honnappa.nagarahalli at arm.com>
 Reviewed-by: Ruifeng Wang <ruifeng.wang at arm.com>
@@ -21,14 +22,57 @@
 Reviewed-by: Phil Yang <phil.yang at arm.com>
 Acked-by: Jerin Jacob <jerinj at marvell.com>
 ---
- lib/librte_eal/arm/include/rte_cycles_64.h | 45 +++++++++++++++++++---
- lib/librte_eal/arm/rte_cycles.c            | 27 +++++++++++--
+ lib/librte_eal/common/arch/arm/rte_cycles.c   | 27 +++++++++--
+ .../common/include/arch/arm/rte_cycles_64.h   | 45 ++++++++++++++++---
  2 files changed, 63 insertions(+), 9 deletions(-)
 
-diff --git a/lib/librte_eal/arm/include/rte_cycles_64.h b/lib/librte_eal/arm/include/rte_cycles_64.h
+diff --git a/lib/librte_eal/common/arch/arm/rte_cycles.c b/lib/librte_eal/common/arch/arm/rte_cycles.c
+index 3500d523e..5bd29b24b 100644
+--- a/lib/librte_eal/common/arch/arm/rte_cycles.c
++++ b/lib/librte_eal/common/arch/arm/rte_cycles.c
+@@ -3,14 +3,35 @@
+  */
+ 
+ #include "eal_private.h"
++#include "rte_cycles.h"
+ 
+ uint64_t
+ get_tsc_freq_arch(void)
+ {
+ #if defined RTE_ARCH_ARM64 && !defined RTE_ARM_EAL_RDTSC_USE_PMU
+-	uint64_t freq;
+-	asm volatile("mrs %0, cntfrq_el0" : "=r" (freq));
+-	return freq;
++	return __rte_arm64_cntfrq();
++#elif defined RTE_ARCH_ARM64 && defined RTE_ARM_EAL_RDTSC_USE_PMU
++#define CYC_PER_1MHZ 1E6
++	/* Use the generic counter ticks to calculate the PMU
++	 * cycle frequency.
++	 */
++	uint64_t ticks;
++	uint64_t start_ticks, cur_ticks;
++	uint64_t start_pmu_cycles, end_pmu_cycles;
++
++	/* Number of ticks for 1/10 second */
++	ticks = __rte_arm64_cntfrq() / 10;
++
++	start_ticks = __rte_arm64_cntvct_precise();
++	start_pmu_cycles = rte_rdtsc_precise();
++	do {
++		cur_ticks = __rte_arm64_cntvct();
++	} while ((cur_ticks - start_ticks) < ticks);
++	end_pmu_cycles = rte_rdtsc_precise();
++
++	/* Adjust the cycles to next 1Mhz */
++	return RTE_ALIGN_MUL_CEIL(end_pmu_cycles - start_pmu_cycles,
++			CYC_PER_1MHZ) * 10;
+ #else
+ 	return 0;
+ #endif
+diff --git a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h
 index da557b6a1..e41f9dbd6 100644
---- a/lib/librte_eal/arm/include/rte_cycles_64.h
-+++ b/lib/librte_eal/arm/include/rte_cycles_64.h
+--- a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h
++++ b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h
 @@ -1,5 +1,6 @@
  /* SPDX-License-Identifier: BSD-3-Clause
   * Copyright(c) 2015 Cavium, Inc
@@ -107,49 +151,6 @@
  #endif
  
  static inline uint64_t
-diff --git a/lib/librte_eal/arm/rte_cycles.c b/lib/librte_eal/arm/rte_cycles.c
-index 3500d523e..5bd29b24b 100644
---- a/lib/librte_eal/arm/rte_cycles.c
-+++ b/lib/librte_eal/arm/rte_cycles.c
-@@ -3,14 +3,35 @@
-  */
- 
- #include "eal_private.h"
-+#include "rte_cycles.h"
- 
- uint64_t
- get_tsc_freq_arch(void)
- {
- #if defined RTE_ARCH_ARM64 && !defined RTE_ARM_EAL_RDTSC_USE_PMU
--	uint64_t freq;
--	asm volatile("mrs %0, cntfrq_el0" : "=r" (freq));
--	return freq;
-+	return __rte_arm64_cntfrq();
-+#elif defined RTE_ARCH_ARM64 && defined RTE_ARM_EAL_RDTSC_USE_PMU
-+#define CYC_PER_1MHZ 1E6
-+	/* Use the generic counter ticks to calculate the PMU
-+	 * cycle frequency.
-+	 */
-+	uint64_t ticks;
-+	uint64_t start_ticks, cur_ticks;
-+	uint64_t start_pmu_cycles, end_pmu_cycles;
-+
-+	/* Number of ticks for 1/10 second */
-+	ticks = __rte_arm64_cntfrq() / 10;
-+
-+	start_ticks = __rte_arm64_cntvct_precise();
-+	start_pmu_cycles = rte_rdtsc_precise();
-+	do {
-+		cur_ticks = __rte_arm64_cntvct();
-+	} while ((cur_ticks - start_ticks) < ticks);
-+	end_pmu_cycles = rte_rdtsc_precise();
-+
-+	/* Adjust the cycles to next 1Mhz */
-+	return RTE_ALIGN_MUL_CEIL(end_pmu_cycles - start_pmu_cycles,
-+			CYC_PER_1MHZ) * 10;
- #else
- 	return 0;
- #endif
 -- 
 2.20.1