[dpdk-stable] patch 'net/octeontx2: enable error and RAS interrupt in configure' has been queued to stable release 19.11.3

[luca.boccassi at gmail.com]

Hi,

FYI, your patch has been queued to stable release 19.11.3

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 05/21/20. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Thanks.

Luca Boccassi

---
>From 6075a1ee65707ee110f4bcab890e7e9ea8d8df6e Mon Sep 17 00:00:00 2001
From: Vamsi Attunuru <vattunuru at marvell.com>
Date: Fri, 3 Apr 2020 07:50:16 +0530
Subject: [PATCH] net/octeontx2: enable error and RAS interrupt in configure

[ upstream commit fdbdf2721c56f49290a45d801b6ac13568a6735b ]

Patch adds routines to set/clear nix lf error & ras interrupt enable
registers. These nix lf error interrupts get triggered if there are
any failures during nix lf configuration. This interrupts are enabled
before any hardware configurations initiated on the allocated nix lf.

Signed-off-by: Vamsi Attunuru <vattunuru at marvell.com>
Acked-by: Andrzej Ostruszka <aostruszka at marvell.com>
Acked-by: Jerin Jacob <jerinj at marvell.com>
---
 drivers/net/octeontx2/otx2_ethdev.c     |  3 +++
 drivers/net/octeontx2/otx2_ethdev.h     |  2 ++
 drivers/net/octeontx2/otx2_ethdev_irq.c | 35 ++++++++++++++++++++-----
 3 files changed, 34 insertions(+), 6 deletions(-)

diff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c
index e450a5ae01..f3281df9c4 100644
--- a/drivers/net/octeontx2/otx2_ethdev.c
+++ b/drivers/net/octeontx2/otx2_ethdev.c
@@ -1650,6 +1650,9 @@ otx2_nix_configure(struct rte_eth_dev *eth_dev)
 		goto fail_offloads;
 	}
 
+	otx2_nix_err_intr_enb_dis(eth_dev, true);
+	otx2_nix_ras_intr_enb_dis(eth_dev, true);
+
 	if (dev->ptp_en &&
 	    dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG) {
 		otx2_err("Both PTP and switch header enabled");
diff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h
index fdc79633e4..864356e36c 100644
--- a/drivers/net/octeontx2/otx2_ethdev.h
+++ b/drivers/net/octeontx2/otx2_ethdev.h
@@ -439,6 +439,8 @@ int oxt2_nix_register_cq_irqs(struct rte_eth_dev *eth_dev);
 void otx2_nix_unregister_irqs(struct rte_eth_dev *eth_dev);
 void oxt2_nix_unregister_queue_irqs(struct rte_eth_dev *eth_dev);
 void oxt2_nix_unregister_cq_irqs(struct rte_eth_dev *eth_dev);
+void otx2_nix_err_intr_enb_dis(struct rte_eth_dev *eth_dev, bool enb);
+void otx2_nix_ras_intr_enb_dis(struct rte_eth_dev *eth_dev, bool enb);
 
 int otx2_nix_rx_queue_intr_enable(struct rte_eth_dev *eth_dev,
 				  uint16_t rx_queue_id);
diff --git a/drivers/net/octeontx2/otx2_ethdev_irq.c b/drivers/net/octeontx2/otx2_ethdev_irq.c
index 2256e40b6f..96b848a919 100644
--- a/drivers/net/octeontx2/otx2_ethdev_irq.c
+++ b/drivers/net/octeontx2/otx2_ethdev_irq.c
@@ -41,11 +41,11 @@ nix_lf_register_err_irq(struct rte_eth_dev *eth_dev)
 	vec = dev->nix_msixoff + NIX_LF_INT_VEC_ERR_INT;
 
 	/* Clear err interrupt */
-	otx2_write64(~0ull, dev->base + NIX_LF_ERR_INT_ENA_W1C);
+	otx2_nix_err_intr_enb_dis(eth_dev, false);
 	/* Set used interrupt vectors */
 	rc = otx2_register_irq(handle, nix_lf_err_irq, eth_dev, vec);
 	/* Enable all dev interrupt except for RQ_DISABLED */
-	otx2_write64(~BIT_ULL(11), dev->base + NIX_LF_ERR_INT_ENA_W1S);
+	otx2_nix_err_intr_enb_dis(eth_dev, true);
 
 	return rc;
 }
@@ -61,7 +61,7 @@ nix_lf_unregister_err_irq(struct rte_eth_dev *eth_dev)
 	vec = dev->nix_msixoff + NIX_LF_INT_VEC_ERR_INT;
 
 	/* Clear err interrupt */
-	otx2_write64(~0ull, dev->base + NIX_LF_ERR_INT_ENA_W1C);
+	otx2_nix_err_intr_enb_dis(eth_dev, false);
 	otx2_unregister_irq(handle, nix_lf_err_irq, eth_dev, vec);
 }
 
@@ -97,11 +97,11 @@ nix_lf_register_ras_irq(struct rte_eth_dev *eth_dev)
 	vec = dev->nix_msixoff + NIX_LF_INT_VEC_POISON;
 
 	/* Clear err interrupt */
-	otx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1C);
+	otx2_nix_ras_intr_enb_dis(eth_dev, false);
 	/* Set used interrupt vectors */
 	rc = otx2_register_irq(handle, nix_lf_ras_irq, eth_dev, vec);
 	/* Enable dev interrupt */
-	otx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1S);
+	otx2_nix_ras_intr_enb_dis(eth_dev, true);
 
 	return rc;
 }
@@ -117,7 +117,7 @@ nix_lf_unregister_ras_irq(struct rte_eth_dev *eth_dev)
 	vec = dev->nix_msixoff + NIX_LF_INT_VEC_POISON;
 
 	/* Clear err interrupt */
-	otx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1C);
+	otx2_nix_ras_intr_enb_dis(eth_dev, false);
 	otx2_unregister_irq(handle, nix_lf_ras_irq, eth_dev, vec);
 }
 
@@ -466,3 +466,26 @@ otx2_nix_rx_queue_intr_disable(struct rte_eth_dev *eth_dev,
 
 	return 0;
 }
+
+void
+otx2_nix_err_intr_enb_dis(struct rte_eth_dev *eth_dev, bool enb)
+{
+	struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
+
+	/* Enable all nix lf error interrupts except for RQ_DISABLED */
+	if (enb)
+		otx2_write64(~BIT_ULL(11), dev->base + NIX_LF_ERR_INT_ENA_W1S);
+	else
+		otx2_write64(~0ull, dev->base + NIX_LF_ERR_INT_ENA_W1C);
+}
+
+void
+otx2_nix_ras_intr_enb_dis(struct rte_eth_dev *eth_dev, bool enb)
+{
+	struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
+
+	if (enb)
+		otx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1S);
+	else
+		otx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1C);
+}
-- 
2.20.1

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2020-05-19 14:04:47.791085258 +0100
+++ 0082-net-octeontx2-enable-error-and-RAS-interrupt-in-conf.patch	2020-05-19 14:04:44.252649025 +0100
@@ -1,8 +1,10 @@
-From fdbdf2721c56f49290a45d801b6ac13568a6735b Mon Sep 17 00:00:00 2001
+From 6075a1ee65707ee110f4bcab890e7e9ea8d8df6e Mon Sep 17 00:00:00 2001
 From: Vamsi Attunuru <vattunuru at marvell.com>
 Date: Fri, 3 Apr 2020 07:50:16 +0530
 Subject: [PATCH] net/octeontx2: enable error and RAS interrupt in configure
 
+[ upstream commit fdbdf2721c56f49290a45d801b6ac13568a6735b ]
+
 Patch adds routines to set/clear nix lf error & ras interrupt enable
 registers. These nix lf error interrupts get triggered if there are
 any failures during nix lf configuration. This interrupts are enabled
@@ -18,10 +20,10 @@
  3 files changed, 34 insertions(+), 6 deletions(-)
 
 diff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c
-index 7202af625c..c56b399af2 100644
+index e450a5ae01..f3281df9c4 100644
 --- a/drivers/net/octeontx2/otx2_ethdev.c
 +++ b/drivers/net/octeontx2/otx2_ethdev.c
-@@ -1666,6 +1666,9 @@ otx2_nix_configure(struct rte_eth_dev *eth_dev)
+@@ -1650,6 +1650,9 @@ otx2_nix_configure(struct rte_eth_dev *eth_dev)
  		goto fail_offloads;
  	}
  
@@ -32,10 +34,10 @@
  	    dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG) {
  		otx2_err("Both PTP and switch header enabled");
 diff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h
-index e5684f9f00..22a4ea9cb6 100644
+index fdc79633e4..864356e36c 100644
 --- a/drivers/net/octeontx2/otx2_ethdev.h
 +++ b/drivers/net/octeontx2/otx2_ethdev.h
-@@ -445,6 +445,8 @@ int oxt2_nix_register_cq_irqs(struct rte_eth_dev *eth_dev);
+@@ -439,6 +439,8 @@ int oxt2_nix_register_cq_irqs(struct rte_eth_dev *eth_dev);
  void otx2_nix_unregister_irqs(struct rte_eth_dev *eth_dev);
  void oxt2_nix_unregister_queue_irqs(struct rte_eth_dev *eth_dev);
  void oxt2_nix_unregister_cq_irqs(struct rte_eth_dev *eth_dev);