[dpdk-stable] patch 'net/octeontx: fix build with SVE' has been queued to stable release 19.11.7

[Christian Ehrhardt]

Hi,

FYI, your patch has been queued to stable release 19.11.7

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 02/06/21. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Queued patches are on a temporary branch at:
https://github.com/cpaelzer/dpdk-stable-queue

This queued commit can be viewed at:
https://github.com/cpaelzer/dpdk-stable-queue/commit/f474bb5284782e3e62f23413884b693040a8b774

Thanks.

Christian Ehrhardt <christian.ehrhardt at canonical.com>

---
>From f474bb5284782e3e62f23413884b693040a8b774 Mon Sep 17 00:00:00 2001
From: Ruifeng Wang <ruifeng.wang at arm.com>
Date: Tue, 12 Jan 2021 02:57:06 +0000
Subject: [PATCH] net/octeontx: fix build with SVE

[ upstream commit e88bd4746737a1ca464b866d29f20ff5a739cd3f ]

Building with gcc 10.2 with SVE extension enabled got error:

{standard input}: Assembler messages:
{standard input}:91: Error: selected processor does not support `addvl x4,x8,#-1'
{standard input}:95: Error: selected processor does not support `ptrue p1.d,all'
{standard input}:135: Error: selected processor does not support `whilelo p2.d,xzr,x5'
{standard input}:137: Error: selected processor does not support `decb x1'

This is because inline assembly code explicitly resets cpu model to
not have SVE support. Thus SVE instructions generated by compiler
auto vectorization got rejected by assembler.

Added SVE to the cpu model specified by inline assembly for SVE support.
Not replacing the inline assembly with C atomics because the driver relies
on specific LSE instruction to interface to co-processor [1].

Fixes: f0c7bb1bf778 ("net/octeontx/base: add octeontx IO operations")

[1] https://mails.dpdk.org/archives/dev/2021-January/196092.html

Signed-off-by: Ruifeng Wang <ruifeng.wang at arm.com>
Reviewed-by: Jerin Jacob <jerinj at marvell.com>
---
 drivers/net/octeontx/base/octeontx_io.h | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/net/octeontx/base/octeontx_io.h b/drivers/net/octeontx/base/octeontx_io.h
index 04b9ce1910..d0b9cfbc67 100644
--- a/drivers/net/octeontx/base/octeontx_io.h
+++ b/drivers/net/octeontx/base/octeontx_io.h
@@ -52,6 +52,11 @@ do {							\
 #endif
 
 #if defined(RTE_ARCH_ARM64)
+#if defined(__ARM_FEATURE_SVE)
+#define __LSE_PREAMBLE " .cpu	generic+lse+sve\n"
+#else
+#define __LSE_PREAMBLE " .cpu	generic+lse\n"
+#endif
 /**
  * Perform an atomic fetch-and-add operation.
  */
@@ -61,7 +66,7 @@ octeontx_reg_ldadd_u64(void *addr, int64_t off)
 	uint64_t old_val;
 
 	__asm__ volatile(
-		" .cpu		generic+lse\n"
+		__LSE_PREAMBLE
 		" ldadd	%1, %0, [%2]\n"
 		: "=r" (old_val) : "r" (off), "r" (addr) : "memory");
 
@@ -98,12 +103,13 @@ octeontx_reg_lmtst(void *lmtline_va, void *ioreg_va, const uint64_t cmdbuf[],
 
 		/* LDEOR initiates atomic transfer to I/O device */
 		__asm__ volatile(
-			" .cpu		generic+lse\n"
+			__LSE_PREAMBLE
 			" ldeor	xzr, %0, [%1]\n"
 			: "=r" (result) : "r" (ioreg_va) : "memory");
 	} while (!result);
 }
 
+#undef __LSE_PREAMBLE
 #else
 
 static inline uint64_t
-- 
2.30.0

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2021-02-04 12:04:29.672059047 +0100
+++ 0037-net-octeontx-fix-build-with-SVE.patch	2021-02-04 12:04:27.946789647 +0100
@@ -1 +1 @@
-From e88bd4746737a1ca464b866d29f20ff5a739cd3f Mon Sep 17 00:00:00 2001
+From f474bb5284782e3e62f23413884b693040a8b774 Mon Sep 17 00:00:00 2001
@@ -5,0 +6,2 @@
+[ upstream commit e88bd4746737a1ca464b866d29f20ff5a739cd3f ]
+
@@ -23 +24,0 @@
-Cc: stable at dpdk.org