[dpdk-stable] [PATCH] [18.11] net/mlx5: fix UAR remap initialization for 32-bit systems
Viacheslav Ovsiienko
viacheslavo at nvidia.com
Sun Jan 17 10:11:17 CET 2021
From: Viacheslav Ovsiienko <viacheslavo at mellanox.com>
The txq_uar_init() routine uses the uninitialized uar_mmap_offset
field in 32-bit configurations due to this field is initialized
after txq_uar_init() call.
Fixes: 9d2cbd9ea8e7 ("net/mlx5: remove device register remap")
Cc: stable at dpdk.org
Signed-off-by: Viacheslav Ovsiienko <viacheslavo at mellanox.com>
Acked-by: Matan Azrad <matan at mellanox.com>
--
Note: there was no patch "net/mlx5: remove device register remap"
in original 18.11, it was backported to 18.11 LTS later.
---
drivers/net/mlx5/mlx5_txq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c
index 862c7a90ec..089f9ab629 100644
--- a/drivers/net/mlx5/mlx5_txq.c
+++ b/drivers/net/mlx5/mlx5_txq.c
@@ -583,7 +583,6 @@ mlx5_txq_ibv_new(struct rte_eth_dev *dev, uint16_t idx)
txq_ibv->cq = tmpl.cq;
rte_atomic32_inc(&txq_ibv->refcnt);
txq_ctrl->bf_reg = qp.bf.reg;
- txq_uar_init(txq_ctrl);
if (qp.comp_mask & MLX5DV_QP_MASK_UAR_MMAP_OFFSET) {
txq_ctrl->uar_mmap_offset = qp.uar_mmap_offset;
DRV_LOG(DEBUG, "port %u: uar_mmap_offset 0x%"PRIx64,
@@ -596,6 +595,7 @@ mlx5_txq_ibv_new(struct rte_eth_dev *dev, uint16_t idx)
rte_errno = EINVAL;
goto error;
}
+ txq_uar_init(txq_ctrl);
LIST_INSERT_HEAD(&priv->txqsibv, txq_ibv, next);
txq_ibv->txq_ctrl = txq_ctrl;
priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
--
2.18.1
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