[PATCH] net/mlx5: remove redundant "set used"

[Ferruh Yigit]

On 11/11/2021 8:59 AM, Slava Ovsiienko wrote:
> Hi, Ferruh
> 
> I've also inspected the mlx5 PMD code for RTE_SET_USED() for the similar
> issues related to the MLX5_ASSERT().
> 
> The patch http://patches.dpdk.org/project/dpdk/patch/20211111084751.26721-1-viacheslavo@nvidia.com/
> should refine the few found ones.
> 
> I do not mind about squashing with "net/mlx5: fix mutex unlock in txpp cleanup"
> After getting this code in Upstream will care about the version for LTS.
> 

It will cause additional complexity for the LTS, since a small part of the below fix
will be originated from Chengfeng's change. To help LTS, what do you think

- First get your fix on top of current task
- Have a new version from Chengfeng on top of latest head, with 'claim_zero' usage?

So only your update need to be merged to LTS releases.



> With best regards,
> Slava
> 
>> -----Original Message-----
>> From: Viacheslav Ovsiienko <viacheslavo at nvidia.com>
>> Sent: Thursday, November 11, 2021 10:48
>> To: dev at dpdk.org
>> Cc: ferruh.yigit at intel.com; Raslan Darawsheh <rasland at nvidia.com>; Matan
>> Azrad <matan at nvidia.com>; stable at dpdk.org
>> Subject: [PATCH] net/mlx5: remove redundant "set used"
>>
>> The patch just refines the code and replaces the pairs of MLX5_ASSERT() and
>> RTE_SET_USED() with equivalent claim_zero().
>>
>> Cc: stable at dpdk.org
>>
>> Signed-off-by: Viacheslav Ovsiienko <viacheslavo at nvidia.com>
>> ---
>>   drivers/net/mlx5/mlx5_txpp.c | 30 ++++++++++--------------------
>>   1 file changed, 10 insertions(+), 20 deletions(-)
>>
>> diff --git a/drivers/net/mlx5/mlx5_txpp.c b/drivers/net/mlx5/mlx5_txpp.c
>> index 73626f0e8f..af77e91e4c 100644
>> --- a/drivers/net/mlx5/mlx5_txpp.c
>> +++ b/drivers/net/mlx5/mlx5_txpp.c
>> @@ -890,7 +890,6 @@ mlx5_txpp_start(struct rte_eth_dev *dev)
>>   	struct mlx5_priv *priv = dev->data->dev_private;
>>   	struct mlx5_dev_ctx_shared *sh = priv->sh;
>>   	int err = 0;
>> -	int ret;
>>
>>   	if (!priv->config.tx_pp) {
>>   		/* Packet pacing is not requested for the device. */ @@ -
>> 903,14 +902,14 @@ mlx5_txpp_start(struct rte_eth_dev *dev)
>>   		return 0;
>>   	}
>>   	if (priv->config.tx_pp > 0) {
>> -		ret = rte_mbuf_dynflag_lookup
>> -
>> 	(RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME, NULL);
>> -		if (ret < 0)
>> +		err = rte_mbuf_dynflag_lookup
>> +			(RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME,
>> NULL);
>> +		/* No flag registered means no service needed. */
>> +		if (err < 0)
>>   			return 0;
>> +		err = 0;
>>   	}
>> -	ret = pthread_mutex_lock(&sh->txpp.mutex);
>> -	MLX5_ASSERT(!ret);
>> -	RTE_SET_USED(ret);
>> +	claim_zero(pthread_mutex_lock(&sh->txpp.mutex));
>>   	if (sh->txpp.refcnt) {
>>   		priv->txpp_en = 1;
>>   		++sh->txpp.refcnt;
>> @@ -924,9 +923,7 @@ mlx5_txpp_start(struct rte_eth_dev *dev)
>>   			rte_errno = -err;
>>   		}
>>   	}
>> -	ret = pthread_mutex_unlock(&sh->txpp.mutex);
>> -	MLX5_ASSERT(!ret);
>> -	RTE_SET_USED(ret);
>> +	claim_zero(pthread_mutex_unlock(&sh->txpp.mutex));
>>   	return err;
>>   }
>>
>> @@ -944,28 +941,21 @@ mlx5_txpp_stop(struct rte_eth_dev *dev)  {
>>   	struct mlx5_priv *priv = dev->data->dev_private;
>>   	struct mlx5_dev_ctx_shared *sh = priv->sh;
>> -	int ret;
>>
>>   	if (!priv->txpp_en) {
>>   		/* Packet pacing is already disabled for the device. */
>>   		return;
>>   	}
>>   	priv->txpp_en = 0;
>> -	ret = pthread_mutex_lock(&sh->txpp.mutex);
>> -	MLX5_ASSERT(!ret);
>> -	RTE_SET_USED(ret);
>> +	claim_zero(pthread_mutex_lock(&sh->txpp.mutex));
>>   	MLX5_ASSERT(sh->txpp.refcnt);
>>   	if (!sh->txpp.refcnt || --sh->txpp.refcnt) {
>> -		ret = pthread_mutex_unlock(&sh->txpp.mutex);
>> -		MLX5_ASSERT(!ret);
>> -		RTE_SET_USED(ret);
>> +		claim_zero(pthread_mutex_unlock(&sh->txpp.mutex));
>>   		return;
>>   	}
>>   	/* No references any more, do actual destroy. */
>>   	mlx5_txpp_destroy(sh);
>> -	ret = pthread_mutex_unlock(&sh->txpp.mutex);
>> -	MLX5_ASSERT(!ret);
>> -	RTE_SET_USED(ret);
>> +	claim_zero(pthread_mutex_unlock(&sh->txpp.mutex));
>>   }
>>
>>   /*
>> --
>> 2.18.1
>