patch 'net/mlx5: fix GRE protocol type translation' has been queued to stable release 20.11.4
Xueming Li
xuemingl at nvidia.com
Sun Nov 28 15:53:52 CET 2021
Hi,
FYI, your patch has been queued to stable release 20.11.4
Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 11/30/21. So please
shout if anyone has objections.
Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.
Queued patches are on a temporary branch at:
https://github.com/steevenlee/dpdk
This queued commit can be viewed at:
https://github.com/steevenlee/dpdk/commit/a12dd597cdabdacf66df697ac60546ad0cbeb401
Thanks.
Xueming Li <xuemingl at nvidia.com>
---
>From a12dd597cdabdacf66df697ac60546ad0cbeb401 Mon Sep 17 00:00:00 2001
From: Gregory Etelson <getelson at nvidia.com>
Date: Sun, 14 Nov 2021 17:36:16 +0200
Subject: [PATCH] net/mlx5: fix GRE protocol type translation
Cc: Xueming Li <xuemingl at nvidia.com>
[ upstream commit be26e81bfc1cb681d3ee0764aa6733000869984a ]
When application creates several flows to match on GRE tunnel
without explicitly specifying GRE protocol type value in
flow rules, PMD will translate that to zero mask.
RDMA-CORE cannot distinguish between different inner flow types and
produces identical matchers for each zero mask.
The patch extracts inner header type from flow rule and forces it
in GRE protocol type, if application did not specify
any without explicitly specifying GRE protocol type value in
flow rules, protocol type value.
Fixes: fc2c498ccb94 ("net/mlx5: add Direct Verbs translate items")
Signed-off-by: Gregory Etelson <getelson at nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo at nvidia.com>
---
drivers/net/mlx5/mlx5_flow_dv.c | 70 +++++++++++++++++++--------------
1 file changed, 40 insertions(+), 30 deletions(-)
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index b80bdc78ba..498b2137f7 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -7001,18 +7001,19 @@ flow_dv_translate_item_gre_key(void *matcher, void *key,
* Flow matcher value.
* @param[in] item
* Flow pattern to translate.
- * @param[in] inner
- * Item is inner pattern.
+ * @param[in] pattern_flags
+ * Accumulated pattern flags.
*/
static void
flow_dv_translate_item_gre(void *matcher, void *key,
const struct rte_flow_item *item,
- int inner)
+ uint64_t pattern_flags)
{
+ static const struct rte_flow_item_gre empty_gre = {0,};
const struct rte_flow_item_gre *gre_m = item->mask;
const struct rte_flow_item_gre *gre_v = item->spec;
- void *headers_m;
- void *headers_v;
+ void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
+ void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
struct {
@@ -7029,26 +7030,17 @@ flow_dv_translate_item_gre(void *matcher, void *key,
uint16_t value;
};
} gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
+ uint16_t protocol_m, protocol_v;
- if (inner) {
- headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
- inner_headers);
- headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
- } else {
- headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
- outer_headers);
- headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
- }
MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
- if (!gre_v)
- return;
- if (!gre_m)
- gre_m = &rte_flow_item_gre_mask;
- MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
- rte_be_to_cpu_16(gre_m->protocol));
- MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
- rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
+ if (!gre_v) {
+ gre_v = &empty_gre;
+ gre_m = &empty_gre;
+ } else {
+ if (!gre_m)
+ gre_m = &rte_flow_item_gre_mask;
+ }
gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
@@ -7066,6 +7058,16 @@ flow_dv_translate_item_gre(void *matcher, void *key,
MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
gre_crks_rsvd0_ver_v.s_present &
gre_crks_rsvd0_ver_m.s_present);
+ protocol_m = rte_be_to_cpu_16(gre_m->protocol);
+ protocol_v = rte_be_to_cpu_16(gre_v->protocol);
+ if (!protocol_m) {
+ /* Force next protocol to prevent matchers duplication */
+ protocol_m = 0xFFFF;
+ protocol_v = mlx5_translate_tunnel_etypes(pattern_flags);
+ }
+ MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, protocol_m);
+ MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
+ protocol_m & protocol_v);
}
/**
@@ -7077,13 +7079,13 @@ flow_dv_translate_item_gre(void *matcher, void *key,
* Flow matcher value.
* @param[in] item
* Flow pattern to translate.
- * @param[in] inner
- * Item is inner pattern.
+ * @param[in] pattern_flags
+ * Accumulated pattern flags.
*/
static void
flow_dv_translate_item_nvgre(void *matcher, void *key,
const struct rte_flow_item *item,
- int inner)
+ unsigned long pattern_flags)
{
const struct rte_flow_item_nvgre *nvgre_m = item->mask;
const struct rte_flow_item_nvgre *nvgre_v = item->spec;
@@ -7110,7 +7112,7 @@ flow_dv_translate_item_nvgre(void *matcher, void *key,
.mask = &gre_mask,
.last = NULL,
};
- flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
+ flow_dv_translate_item_gre(matcher, key, &gre_item, pattern_flags);
if (!nvgre_v)
return;
if (!nvgre_m)
@@ -10547,10 +10549,9 @@ flow_dv_translate(struct rte_eth_dev *dev,
MLX5_FLOW_LAYER_OUTER_L4_UDP;
break;
case RTE_FLOW_ITEM_TYPE_GRE:
- flow_dv_translate_item_gre(match_mask, match_value,
- items, tunnel);
matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
last_item = MLX5_FLOW_LAYER_GRE;
+ tunnel_item = items;
break;
case RTE_FLOW_ITEM_TYPE_GRE_KEY:
flow_dv_translate_item_gre_key(match_mask,
@@ -10558,10 +10559,9 @@ flow_dv_translate(struct rte_eth_dev *dev,
last_item = MLX5_FLOW_LAYER_GRE_KEY;
break;
case RTE_FLOW_ITEM_TYPE_NVGRE:
- flow_dv_translate_item_nvgre(match_mask, match_value,
- items, tunnel);
matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
last_item = MLX5_FLOW_LAYER_GRE;
+ tunnel_item = items;
break;
case RTE_FLOW_ITEM_TYPE_VXLAN:
flow_dv_translate_item_vxlan(match_mask, match_value,
@@ -10672,6 +10672,16 @@ flow_dv_translate(struct rte_eth_dev *dev,
else if (item_flags & MLX5_FLOW_LAYER_GENEVE)
flow_dv_translate_item_geneve(match_mask, match_value,
tunnel_item, item_flags);
+ else if (item_flags & MLX5_FLOW_LAYER_GRE) {
+ if (tunnel_item->type == RTE_FLOW_ITEM_TYPE_GRE)
+ flow_dv_translate_item_gre(match_mask, match_value,
+ tunnel_item, item_flags);
+ else if (tunnel_item->type == RTE_FLOW_ITEM_TYPE_NVGRE)
+ flow_dv_translate_item_nvgre(match_mask, match_value,
+ tunnel_item, item_flags);
+ else
+ MLX5_ASSERT(false);
+ }
#ifdef RTE_LIBRTE_MLX5_DEBUG
MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
dev_flow->dv.value.buf));
--
2.34.0
---
Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- - 2021-11-28 22:41:05.810489890 +0800
+++ 0048-net-mlx5-fix-GRE-protocol-type-translation.patch 2021-11-28 22:41:03.366873469 +0800
@@ -1 +1 @@
-From be26e81bfc1cb681d3ee0764aa6733000869984a Mon Sep 17 00:00:00 2001
+From a12dd597cdabdacf66df697ac60546ad0cbeb401 Mon Sep 17 00:00:00 2001
@@ -4,0 +5,3 @@
+Cc: Xueming Li <xuemingl at nvidia.com>
+
+[ upstream commit be26e81bfc1cb681d3ee0764aa6733000869984a ]
@@ -18 +20,0 @@
-Cc: stable at dpdk.org
@@ -27 +29 @@
-index bce504391d..287a17d956 100644
+index b80bdc78ba..498b2137f7 100644
@@ -30 +32 @@
-@@ -8730,18 +8730,19 @@ flow_dv_translate_item_gre_key(void *matcher, void *key,
+@@ -7001,18 +7001,19 @@ flow_dv_translate_item_gre_key(void *matcher, void *key,
@@ -55 +57 @@
-@@ -8758,26 +8759,17 @@ flow_dv_translate_item_gre(void *matcher, void *key,
+@@ -7029,26 +7030,17 @@ flow_dv_translate_item_gre(void *matcher, void *key,
@@ -90 +92 @@
-@@ -8795,6 +8787,16 @@ flow_dv_translate_item_gre(void *matcher, void *key,
+@@ -7066,6 +7058,16 @@ flow_dv_translate_item_gre(void *matcher, void *key,
@@ -107 +109 @@
-@@ -8806,13 +8808,13 @@ flow_dv_translate_item_gre(void *matcher, void *key,
+@@ -7077,13 +7079,13 @@ flow_dv_translate_item_gre(void *matcher, void *key,
@@ -124 +126 @@
-@@ -8839,7 +8841,7 @@ flow_dv_translate_item_nvgre(void *matcher, void *key,
+@@ -7110,7 +7112,7 @@ flow_dv_translate_item_nvgre(void *matcher, void *key,
@@ -133 +135 @@
-@@ -13434,10 +13436,9 @@ flow_dv_translate(struct rte_eth_dev *dev,
+@@ -10547,10 +10549,9 @@ flow_dv_translate(struct rte_eth_dev *dev,
@@ -145 +147 @@
-@@ -13445,10 +13446,9 @@ flow_dv_translate(struct rte_eth_dev *dev,
+@@ -10558,10 +10559,9 @@ flow_dv_translate(struct rte_eth_dev *dev,
@@ -156,2 +158,2 @@
- flow_dv_translate_item_vxlan(dev, attr,
-@@ -13597,6 +13597,16 @@ flow_dv_translate(struct rte_eth_dev *dev,
+ flow_dv_translate_item_vxlan(match_mask, match_value,
+@@ -10672,6 +10672,16 @@ flow_dv_translate(struct rte_eth_dev *dev,
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