patch 'net/iavf: count continuous DD bits for Arm' has been queued to stable release 21.11.1

[Kevin Traynor]

Hi,

FYI, your patch has been queued to stable release 21.11.1

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 02/26/22. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Queued patches are on a temporary branch at:
https://github.com/kevintraynor/dpdk-stable

This queued commit can be viewed at:
https://github.com/kevintraynor/dpdk-stable/commit/68522027e305f1199758c7e644ba063ef4ff763d

Thanks.

Kevin

---
>From 68522027e305f1199758c7e644ba063ef4ff763d Mon Sep 17 00:00:00 2001
From: Kathleen Capella <kathleen.capella at arm.com>
Date: Sat, 5 Feb 2022 00:26:29 +0000
Subject: [PATCH] net/iavf: count continuous DD bits for Arm

[ upstream commit 3d88d5e401f6d04882415866012a98bced0c3cb8 ]

On Arm platforms, reading of descriptors may be re-ordered causing the
status of DD bits to be discontinuous. Add logic to only process
continuous descriptors by checking DD bits.

Fixes: 1060591eada5 ("net/avf: enable bulk allocate Rx")

Signed-off-by: Kathleen Capella <kathleen.capella at arm.com>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli at arm.com>
Reviewed-by: Qi Zhang <qi.z.zhang at intel.com>
---
 drivers/net/iavf/iavf_rxtx.c | 26 ++++++++++++++++++++++----
 1 file changed, 22 insertions(+), 4 deletions(-)

diff --git a/drivers/net/iavf/iavf_rxtx.c b/drivers/net/iavf/iavf_rxtx.c
index 59623ac820..4fc1bf5e78 100644
--- a/drivers/net/iavf/iavf_rxtx.c
+++ b/drivers/net/iavf/iavf_rxtx.c
@@ -1899,5 +1899,5 @@ iavf_rx_scan_hw_ring(struct iavf_rx_queue *rxq)
 	uint64_t qword1;
 	uint32_t rx_status;
-	int32_t s[IAVF_LOOK_AHEAD], nb_dd;
+	int32_t s[IAVF_LOOK_AHEAD], var, nb_dd;
 	int32_t i, j, nb_rx = 0;
 	uint64_t pkt_flags;
@@ -1930,7 +1930,25 @@ iavf_rx_scan_hw_ring(struct iavf_rx_queue *rxq)
 		rte_smp_rmb();
 
-		/* Compute how many status bits were set */
-		for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++)
-			nb_dd += s[j] & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
+		/* Compute how many contiguous DD bits were set */
+		for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++) {
+			var = s[j] & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
+#ifdef RTE_ARCH_ARM
+			/* For Arm platforms, count only contiguous descriptors
+			 * whose DD bit is set to 1. On Arm platforms, reads of
+			 * descriptors can be reordered. Since the CPU may
+			 * be reading the descriptors as the NIC updates them
+			 * in memory, it is possbile that the DD bit for a
+			 * descriptor earlier in the queue is read as not set
+			 * while the DD bit for a descriptor later in the queue
+			 * is read as set.
+			 */
+			if (var)
+				nb_dd += 1;
+			else
+				break;
+#else
+			nb_dd += var;
+#endif
+		}
 
 		nb_rx += nb_dd;
-- 
2.34.1

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2022-02-21 15:22:48.139456937 +0000
+++ 0166-net-iavf-count-continuous-DD-bits-for-Arm.patch	2022-02-21 15:22:44.319704639 +0000
@@ -1 +1 @@
-From 3d88d5e401f6d04882415866012a98bced0c3cb8 Mon Sep 17 00:00:00 2001
+From 68522027e305f1199758c7e644ba063ef4ff763d Mon Sep 17 00:00:00 2001
@@ -5,0 +6,2 @@
+[ upstream commit 3d88d5e401f6d04882415866012a98bced0c3cb8 ]
+
@@ -11 +12,0 @@
-Cc: stable at dpdk.org
@@ -21 +22 @@
-index 7158938643..f07d886821 100644
+index 59623ac820..4fc1bf5e78 100644
@@ -24 +25 @@
-@@ -1898,5 +1898,5 @@ iavf_rx_scan_hw_ring(struct iavf_rx_queue *rxq)
+@@ -1899,5 +1899,5 @@ iavf_rx_scan_hw_ring(struct iavf_rx_queue *rxq)
@@ -31 +32 @@
-@@ -1929,7 +1929,25 @@ iavf_rx_scan_hw_ring(struct iavf_rx_queue *rxq)
+@@ -1930,7 +1930,25 @@ iavf_rx_scan_hw_ring(struct iavf_rx_queue *rxq)