[PATCH v2] net/iavf: fix Rx queue interrupt setting
Ke Zhang
ke1x.zhang at intel.com
Thu May 19 11:30:31 CEST 2022
For Rx-Queue Interrupt Setting, when vf rx interrupt
disable(INTENA=0), there are two ways to write back
descriptor to host memory:
1)Set WB_ON_ITR bit 0 to Interrupt Dynamic Control Register:
Completed descriptors are posted to host memory according to
the internal descriptor cache policy (in other words when a
full cache line is available for write-back).
2)Set WB_ON_ITR bit 1 to Interrupt Dynamic Control Register:
Completed descriptors also trigger the ITR. Following ITR
expiration, all leftover completed descriptors are posted to
host memory.
Changing 1) to 2) to make sure VF synchronizing with PF.
Fixes: d6bde6b5eae9 ("net/avf: enable Rx interrupt")
Cc: stable at dpdk.org
Signed-off-by: Ke Zhang <ke1x.zhang at intel.com>
---
drivers/net/iavf/iavf_ethdev.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/iavf/iavf_ethdev.c b/drivers/net/iavf/iavf_ethdev.c
index d6190ac24a..17c7720600 100644
--- a/drivers/net/iavf/iavf_ethdev.c
+++ b/drivers/net/iavf/iavf_ethdev.c
@@ -1833,7 +1833,7 @@ iavf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
IAVF_WRITE_REG(hw,
IAVF_VFINT_DYN_CTLN1(msix_intr - IAVF_RX_VEC_START),
- 0);
+ IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_MASK);
IAVF_WRITE_FLUSH(hw);
return 0;
--
2.25.1
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