[PATCH v2] net/iavf: fix Rx queue interrupt setting

[Zhang, Qi Z]

> -----Original Message-----
> From: Ke Zhang <ke1x.zhang at intel.com>
> Sent: Friday, May 20, 2022 11:00 AM
> To: Li, Xiaoyun <xiaoyun.li at intel.com>; Wu, Jingjing <jingjing.wu at intel.com>;
> Xing, Beilei <beilei.xing at intel.com>; dev at dpdk.org
> Cc: Zhang, Ke1X <ke1x.zhang at intel.com>; stable at dpdk.org
> Subject: [PATCH v2] net/iavf: fix Rx queue interrupt setting
>
> For Rx-Queue Interrupt Setting, when vf rx interrupt disable(INTENA=0), there
> are two ways to write back descriptor to host memory:
>
> 1)Set WB_ON_ITR bit 0 to Interrupt Dynamic Control Register:
> Completed descriptors are posted to host memory according to the internal
> descriptor cache policy (in other words when a full cache line is available for
> write-back).
>
> A internal descriptor size is 16 bytes or 32 bytes, a cache line size is 64 bytes or
> 128 bytes from datasheet :
> PCIe Global Config 2 - GLPCI_CNF2 (0x000BE004; RO) so the full cache line
> could contains 4 packets, it means Network card will send 4 packets to host
> when a full cache line is available.
>
> 2)Set WB_ON_ITR bit 1 to Interrupt Dynamic Control Register:
> Completed descriptors also trigger the ITR. Following ITR expiration, all
> leftover completed descriptors are posted to host memory.
>
> Network card will send packet to host even if only one descriptor is completed.
>
> Changing 1) to 2) to make sure VF send the packet to host even if there is only
> one rx packet is ready in hardware.
>
> Fixes: d6bde6b5eae9 ("net/avf: enable Rx interrupt")
> Cc: stable at dpdk.org
>
> Signed-off-by: Ke Zhang <ke1x.zhang at intel.com>

Acked-by: Qi Zhang <qi.z.zhang at intel.com>

Applied to dpdk-next-net-intel.

Thanks
Qi