patch 'common/cnxk: fix SQ flush sequence' has been queued to stable release 21.11.2

[Kevin Traynor]

Hi,

FYI, your patch has been queued to stable release 21.11.2

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 05/30/22. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Queued patches are on a temporary branch at:
https://github.com/kevintraynor/dpdk-stable

This queued commit can be viewed at:
https://github.com/kevintraynor/dpdk-stable/commit/8790891a6dac401fe968022272e31a14d6b99fb9

Thanks.

Kevin

---
>From 8790891a6dac401fe968022272e31a14d6b99fb9 Mon Sep 17 00:00:00 2001
From: Satha Rao <skoteshwar at marvell.com>
Date: Sun, 8 May 2022 13:18:16 +0530
Subject: [PATCH] common/cnxk: fix SQ flush sequence

[ upstream commit e746aec161cc5642935e1ac4b823bdb2d722ec27 ]

Fix SQ flush sequence to issue NIX RX SW Sync after SMQ flush.
This sync ensures that all the packets that were in-flight are
flushed out of memory.

This patch also fixes NULL return issues reported by
static analysis tool in Traffic Manager and sync's mailbox
to that of the kernel version.

Fixes: 05d727e8b14a ("common/cnxk: support NIX traffic management")
Fixes: 0b7e667ee303 ("common/cnxk: enable packet marking")

Signed-off-by: Satha Rao <skoteshwar at marvell.com>
Acked-by: Jerin Jacob <jerinj at marvell.com>
---
 drivers/common/cnxk/roc_mbox.h   | 35 ++++++++++++++++++++++++++++++--
 drivers/common/cnxk/roc_nix_tm.c |  7 +++++++
 2 files changed, 40 insertions(+), 2 deletions(-)

diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index b63fe108c9..9a8ae6b216 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -115,5 +115,5 @@ struct mbox_msghdr {
 	M(SSO_GRP_GET_PRIORITY, 0x606, sso_grp_get_priority, sso_info_req,     \
 	  sso_grp_priority)                                                    \
-	M(SSO_WS_CACHE_INV, 0x607, sso_ws_cache_inv, msg_req, msg_rsp)         \
+	M(SSO_WS_CACHE_INV, 0x607, sso_ws_cache_inv, ssow_lf_inv_req, msg_rsp) \
 	M(SSO_GRP_QOS_CONFIG, 0x608, sso_grp_qos_config, sso_grp_qos_cfg,      \
 	  msg_rsp)                                                             \
@@ -124,4 +124,7 @@ struct mbox_msghdr {
 	M(SSO_HW_RELEASE_XAQ, 0x611, sso_hw_release_xaq_aura,                  \
 	  sso_hw_xaq_release, msg_rsp)                                         \
+	M(SSO_CONFIG_LSW, 0x612, ssow_config_lsw, ssow_config_lsw, msg_rsp)    \
+	M(SSO_HWS_CHNG_MSHIP, 0x613, ssow_chng_mship, ssow_chng_mship,         \
+	  msg_rsp)                                                             \
 	/* TIM mbox IDs (range 0x800 - 0x9FF) */                               \
 	M(TIM_LF_ALLOC, 0x800, tim_lf_alloc, tim_lf_alloc_req,                 \
@@ -248,5 +251,6 @@ struct mbox_msghdr {
 	  nix_bp_cfg_rsp)                                                      \
 	M(NIX_CPT_BP_DISABLE, 0x8021, nix_cpt_bp_disable, nix_bp_cfg_req,      \
-	  msg_rsp)
+	  msg_rsp)                                                             \
+	M(NIX_RX_SW_SYNC, 0x8022, nix_rx_sw_sync, msg_req, msg_rsp)
 
 /* Messages initiated by AF (range 0xC00 - 0xDFF) */
@@ -1241,4 +1245,31 @@ struct ssow_lf_free_req {
 };
 
+#define SSOW_INVAL_SELECTIVE_VER 0x1000
+struct ssow_lf_inv_req {
+	struct mbox_msghdr hdr;
+	uint16_t nb_hws;		 /* Number of HWS to invalidate*/
+	uint16_t hws[MAX_RVU_BLKLF_CNT]; /* Array of HWS */
+};
+
+struct ssow_config_lsw {
+	struct mbox_msghdr hdr;
+#define SSOW_LSW_DIS	 0
+#define SSOW_LSW_GW_WAIT 1
+#define SSOW_LSW_GW_IMM	 2
+	uint8_t __io lsw_mode;
+#define SSOW_WQE_REL_LSW_WAIT 0
+#define SSOW_WQE_REL_IMM      1
+	uint8_t __io wqe_release;
+};
+
+struct ssow_chng_mship {
+	struct mbox_msghdr hdr;
+	uint8_t __io set;	 /* Membership set to modify. */
+	uint8_t __io enable;	 /* Enable/Disable the hwgrps. */
+	uint8_t __io hws;	 /* HWS to modify. */
+	uint16_t __io nb_hwgrps; /* Number of hwgrps in the array */
+	uint16_t __io hwgrps[MAX_RVU_BLKLF_CNT]; /* Array of hwgrps. */
+};
+
 struct sso_hw_setconfig {
 	struct mbox_msghdr hdr;
diff --git a/drivers/common/cnxk/roc_nix_tm.c b/drivers/common/cnxk/roc_nix_tm.c
index ebb27a3106..506cb066ce 100644
--- a/drivers/common/cnxk/roc_nix_tm.c
+++ b/drivers/common/cnxk/roc_nix_tm.c
@@ -565,4 +565,5 @@ nix_tm_sq_flush_pre(struct roc_nix_sq *sq)
 	struct nix_tm_node_list *list;
 	enum roc_nix_tm_tree tree;
+	struct msg_req *req;
 	struct mbox *mbox;
 	struct nix *nix;
@@ -654,4 +655,10 @@ nix_tm_sq_flush_pre(struct roc_nix_sq *sq)
 		goto cleanup;
 	}
+
+	req = mbox_alloc_msg_nix_rx_sw_sync(mbox);
+	if (!req)
+		return -ENOSPC;
+
+	rc = mbox_process(mbox);
 cleanup:
 	/* Restore cgx state */
-- 
2.34.3

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2022-05-25 17:26:59.394662975 +0100
+++ 0034-common-cnxk-fix-SQ-flush-sequence.patch	2022-05-25 17:26:58.614828400 +0100
@@ -1 +1 @@
-From e746aec161cc5642935e1ac4b823bdb2d722ec27 Mon Sep 17 00:00:00 2001
+From 8790891a6dac401fe968022272e31a14d6b99fb9 Mon Sep 17 00:00:00 2001
@@ -5,0 +6,2 @@
+[ upstream commit e746aec161cc5642935e1ac4b823bdb2d722ec27 ]
+
@@ -16 +17,0 @@
-Cc: stable at dpdk.org
@@ -21,4 +22,3 @@
- drivers/common/cnxk/roc_mbox.h        | 35 +++++++++++++++++++++++++--
- drivers/common/cnxk/roc_nix_tm.c      |  7 ++++++
- drivers/common/cnxk/roc_nix_tm_mark.c |  9 +++++++
- 3 files changed, 49 insertions(+), 2 deletions(-)
+ drivers/common/cnxk/roc_mbox.h   | 35 ++++++++++++++++++++++++++++++--
+ drivers/common/cnxk/roc_nix_tm.c |  7 +++++++
+ 2 files changed, 40 insertions(+), 2 deletions(-)
@@ -27 +27 @@
-index b608f58357..2c30f19904 100644
+index b63fe108c9..9a8ae6b216 100644
@@ -30 +30 @@
-@@ -117,5 +117,5 @@ struct mbox_msghdr {
+@@ -115,5 +115,5 @@ struct mbox_msghdr {
@@ -37 +37 @@
-@@ -126,4 +126,7 @@ struct mbox_msghdr {
+@@ -124,4 +124,7 @@ struct mbox_msghdr {
@@ -45 +45 @@
-@@ -260,5 +263,6 @@ struct mbox_msghdr {
+@@ -248,5 +251,6 @@ struct mbox_msghdr {
@@ -53 +53 @@
-@@ -1269,4 +1273,31 @@ struct ssow_lf_free_req {
+@@ -1241,4 +1245,31 @@ struct ssow_lf_free_req {
@@ -86 +86 @@
-index 5b70c7bfed..42d3abd070 100644
+index ebb27a3106..506cb066ce 100644
@@ -89 +89 @@
-@@ -591,4 +591,5 @@ nix_tm_sq_flush_pre(struct roc_nix_sq *sq)
+@@ -565,4 +565,5 @@ nix_tm_sq_flush_pre(struct roc_nix_sq *sq)
@@ -95 +95 @@
-@@ -680,4 +681,10 @@ nix_tm_sq_flush_pre(struct roc_nix_sq *sq)
+@@ -654,4 +655,10 @@ nix_tm_sq_flush_pre(struct roc_nix_sq *sq)
@@ -106,28 +105,0 @@
-diff --git a/drivers/common/cnxk/roc_nix_tm_mark.c b/drivers/common/cnxk/roc_nix_tm_mark.c
-index 64cf67943a..d37292e8b9 100644
---- a/drivers/common/cnxk/roc_nix_tm_mark.c
-+++ b/drivers/common/cnxk/roc_nix_tm_mark.c
-@@ -111,4 +111,7 @@ nix_tm_update_red_algo(struct nix *nix, bool red_send)
- 		/* Update txschq config  */
- 		req = mbox_alloc_msg_nix_txschq_cfg(mbox);
-+		if (req == NULL)
-+			return -ENOSPC;
-+
- 		req->lvl = tm_node->hw_lvl;
- 		k = prepare_tm_shaper_red_algo(tm_node, req->reg, req->regval,
-@@ -209,4 +212,7 @@ nix_tm_mark_init(struct nix *nix)
- 	/* Null mark format */
- 	req = mbox_alloc_msg_nix_mark_format_cfg(mbox);
-+	if (req == NULL)
-+		return -ENOSPC;
-+
- 	rc = mbox_process_msg(mbox, (void *)&rsp);
- 	if (rc) {
-@@ -221,4 +227,7 @@ nix_tm_mark_init(struct nix *nix)
- 		for (j = 0; j < ROC_NIX_TM_MARK_COLOR_MAX; j++) {
- 			req = mbox_alloc_msg_nix_mark_format_cfg(mbox);
-+			if (req == NULL)
-+				return -ENOSPC;
-+
- 			req->offset = mark_off[i];
-