patch 'net/mlx5: fix check for orphan wait descriptor' has been queued to stable release 21.11.3
Kevin Traynor
ktraynor at redhat.com
Tue Oct 25 17:07:01 CEST 2022
Hi,
FYI, your patch has been queued to stable release 21.11.3
Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 11/01/22. So please
shout if anyone has objections.
Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.
Queued patches are on a temporary branch at:
https://github.com/kevintraynor/dpdk-stable
This queued commit can be viewed at:
https://github.com/kevintraynor/dpdk-stable/commit/b5e5d926b224bdda168d2d9fd2d8cce0e5dbcec0
Thanks.
Kevin
---
>From b5e5d926b224bdda168d2d9fd2d8cce0e5dbcec0 Mon Sep 17 00:00:00 2001
From: Viacheslav Ovsiienko <viacheslavo at nvidia.com>
Date: Thu, 11 Aug 2022 08:50:58 +0300
Subject: [PATCH] net/mlx5: fix check for orphan wait descriptor
[ upstream commit 37d6fc30c1ad03485ef707140b67623b95498d0d ]
The mlx5 PMD supports send scheduling feature, it allows
to send packets at specified moment of time, to do that
PMD pushes special wait descriptor (WQE) to the hardware
queue and then pushes descriptor for packet data as usual.
If queue is close to be full or there is no enough elts
buffers to store mbufs being sent the data descriptors might
be not pushed and the orphan wait WQE (not followed by the
data) might reside in queue on tx_burst routine exit.
To avoid orphan wait WQEs there was the check for enough
free space in the queue WQE buffer and enough amount of the
free elts in queue mbuf storage. This check was incomplete
and did not cover all the cases for Enhanced Multi-Packet
Write descriptors.
Fixes: 2f827f5ea6e1 ("net/mlx5: support scheduling on send routine template")
Signed-off-by: Viacheslav Ovsiienko <viacheslavo at nvidia.com>
---
drivers/net/mlx5/mlx5_tx.h | 78 +++++++++++++++++++++-----------------
1 file changed, 43 insertions(+), 35 deletions(-)
diff --git a/drivers/net/mlx5/mlx5_tx.h b/drivers/net/mlx5/mlx5_tx.h
index 6ed00f722e..bd3a060963 100644
--- a/drivers/net/mlx5/mlx5_tx.h
+++ b/drivers/net/mlx5/mlx5_tx.h
@@ -1623,4 +1623,5 @@ static __rte_always_inline enum mlx5_txcmp_code
mlx5_tx_schedule_send(struct mlx5_txq_data *restrict txq,
struct mlx5_txq_local *restrict loc,
+ uint16_t elts,
unsigned int olx)
{
@@ -1637,5 +1638,5 @@ mlx5_tx_schedule_send(struct mlx5_txq_data *restrict txq,
*/
if (loc->wqe_free <= MLX5_WQE_SIZE_MAX / MLX5_WQE_SIZE ||
- loc->elts_free < NB_SEGS(loc->mbuf))
+ loc->elts_free < elts)
return MLX5_TXCMP_CODE_EXIT;
/* Convert the timestamp into completion to wait. */
@@ -1667,4 +1668,7 @@ mlx5_tx_schedule_send(struct mlx5_txq_data *restrict txq,
* @param loc
* Pointer to burst routine local context.
+ * @param elts
+ * Number of free elements in elts buffer to be checked, for zero
+ * value the check is optimized out by compiler.
* @param olx
* Configured Tx offloads mask. It is fully defined at
@@ -1684,9 +1688,10 @@ mlx5_tx_packet_multi_tso(struct mlx5_txq_data *__rte_restrict txq,
unsigned int ds, dlen, inlen, ntcp, vlan = 0;
+ MLX5_ASSERT(loc->elts_free >= NB_SEGS(loc->mbuf));
if (MLX5_TXOFF_CONFIG(TXPP)) {
enum mlx5_txcmp_code wret;
/* Generate WAIT for scheduling if requested. */
- wret = mlx5_tx_schedule_send(txq, loc, olx);
+ wret = mlx5_tx_schedule_send(txq, loc, 0, olx);
if (wret == MLX5_TXCMP_CODE_EXIT)
return MLX5_TXCMP_CODE_EXIT;
@@ -1782,9 +1787,10 @@ mlx5_tx_packet_multi_send(struct mlx5_txq_data *__rte_restrict txq,
MLX5_ASSERT(NB_SEGS(loc->mbuf) > 1);
+ MLX5_ASSERT(loc->elts_free >= NB_SEGS(loc->mbuf));
if (MLX5_TXOFF_CONFIG(TXPP)) {
enum mlx5_txcmp_code wret;
/* Generate WAIT for scheduling if requested. */
- wret = mlx5_tx_schedule_send(txq, loc, olx);
+ wret = mlx5_tx_schedule_send(txq, loc, 0, olx);
if (wret == MLX5_TXCMP_CODE_EXIT)
return MLX5_TXCMP_CODE_EXIT;
@@ -1897,14 +1903,5 @@ mlx5_tx_packet_multi_inline(struct mlx5_txq_data *__rte_restrict txq,
MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
MLX5_ASSERT(NB_SEGS(loc->mbuf) > 1);
- if (MLX5_TXOFF_CONFIG(TXPP)) {
- enum mlx5_txcmp_code wret;
-
- /* Generate WAIT for scheduling if requested. */
- wret = mlx5_tx_schedule_send(txq, loc, olx);
- if (wret == MLX5_TXCMP_CODE_EXIT)
- return MLX5_TXCMP_CODE_EXIT;
- if (wret == MLX5_TXCMP_CODE_ERROR)
- return MLX5_TXCMP_CODE_ERROR;
- }
+ MLX5_ASSERT(loc->elts_free >= NB_SEGS(loc->mbuf));
/*
* First calculate data length to be inlined
@@ -2012,4 +2009,14 @@ do_align:
*/
do_build:
+ if (MLX5_TXOFF_CONFIG(TXPP)) {
+ enum mlx5_txcmp_code wret;
+
+ /* Generate WAIT for scheduling if requested. */
+ wret = mlx5_tx_schedule_send(txq, loc, 0, olx);
+ if (wret == MLX5_TXCMP_CODE_EXIT)
+ return MLX5_TXCMP_CODE_EXIT;
+ if (wret == MLX5_TXCMP_CODE_ERROR)
+ return MLX5_TXCMP_CODE_ERROR;
+ }
MLX5_ASSERT(inlen <= txq->inlen_send);
ds = NB_SEGS(loc->mbuf) + 2 + (inlen -
@@ -2172,5 +2179,5 @@ mlx5_tx_burst_tso(struct mlx5_txq_data *__rte_restrict txq,
/* Generate WAIT for scheduling if requested. */
- wret = mlx5_tx_schedule_send(txq, loc, olx);
+ wret = mlx5_tx_schedule_send(txq, loc, 1, olx);
if (wret == MLX5_TXCMP_CODE_EXIT)
return MLX5_TXCMP_CODE_EXIT;
@@ -2550,14 +2557,4 @@ mlx5_tx_burst_empw_simple(struct mlx5_txq_data *__rte_restrict txq,
next_empw:
MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
- if (MLX5_TXOFF_CONFIG(TXPP)) {
- enum mlx5_txcmp_code wret;
-
- /* Generate WAIT for scheduling if requested. */
- wret = mlx5_tx_schedule_send(txq, loc, olx);
- if (wret == MLX5_TXCMP_CODE_EXIT)
- return MLX5_TXCMP_CODE_EXIT;
- if (wret == MLX5_TXCMP_CODE_ERROR)
- return MLX5_TXCMP_CODE_ERROR;
- }
part = RTE_MIN(pkts_n, MLX5_TXOFF_CONFIG(MPW) ?
MLX5_MPW_MAX_PACKETS :
@@ -2570,4 +2567,14 @@ next_empw:
part = loc->elts_free;
}
+ if (MLX5_TXOFF_CONFIG(TXPP)) {
+ enum mlx5_txcmp_code wret;
+
+ /* Generate WAIT for scheduling if requested. */
+ wret = mlx5_tx_schedule_send(txq, loc, 0, olx);
+ if (wret == MLX5_TXCMP_CODE_EXIT)
+ return MLX5_TXCMP_CODE_EXIT;
+ if (wret == MLX5_TXCMP_CODE_ERROR)
+ return MLX5_TXCMP_CODE_ERROR;
+ }
/* Check whether we have enough WQEs */
if (unlikely(loc->wqe_free < ((2 + part + 3) / 4))) {
@@ -2724,14 +2731,4 @@ mlx5_tx_burst_empw_inline(struct mlx5_txq_data *__rte_restrict txq,
MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
- if (MLX5_TXOFF_CONFIG(TXPP)) {
- enum mlx5_txcmp_code wret;
-
- /* Generate WAIT for scheduling if requested. */
- wret = mlx5_tx_schedule_send(txq, loc, olx);
- if (wret == MLX5_TXCMP_CODE_EXIT)
- return MLX5_TXCMP_CODE_EXIT;
- if (wret == MLX5_TXCMP_CODE_ERROR)
- return MLX5_TXCMP_CODE_ERROR;
- }
/*
* Limits the amount of packets in one WQE
@@ -2741,4 +2738,14 @@ mlx5_tx_burst_empw_inline(struct mlx5_txq_data *__rte_restrict txq,
MLX5_MPW_INLINE_MAX_PACKETS :
MLX5_EMPW_MAX_PACKETS);
+ if (MLX5_TXOFF_CONFIG(TXPP)) {
+ enum mlx5_txcmp_code wret;
+
+ /* Generate WAIT for scheduling if requested. */
+ wret = mlx5_tx_schedule_send(txq, loc, nlim, olx);
+ if (wret == MLX5_TXCMP_CODE_EXIT)
+ return MLX5_TXCMP_CODE_EXIT;
+ if (wret == MLX5_TXCMP_CODE_ERROR)
+ return MLX5_TXCMP_CODE_ERROR;
+ }
/* Check whether we have minimal amount WQEs */
if (unlikely(loc->wqe_free <
@@ -3023,9 +3030,10 @@ mlx5_tx_burst_single_send(struct mlx5_txq_data *__rte_restrict txq,
MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
+ MLX5_ASSERT(loc->elts_free);
if (MLX5_TXOFF_CONFIG(TXPP)) {
enum mlx5_txcmp_code wret;
/* Generate WAIT for scheduling if requested. */
- wret = mlx5_tx_schedule_send(txq, loc, olx);
+ wret = mlx5_tx_schedule_send(txq, loc, 0, olx);
if (wret == MLX5_TXCMP_CODE_EXIT)
return MLX5_TXCMP_CODE_EXIT;
--
2.37.3
---
Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- - 2022-10-25 14:19:00.039429874 +0100
+++ 0066-net-mlx5-fix-check-for-orphan-wait-descriptor.patch 2022-10-25 14:18:58.473798313 +0100
@@ -1 +1 @@
-From 37d6fc30c1ad03485ef707140b67623b95498d0d Mon Sep 17 00:00:00 2001
+From b5e5d926b224bdda168d2d9fd2d8cce0e5dbcec0 Mon Sep 17 00:00:00 2001
@@ -5,0 +6,2 @@
+[ upstream commit 37d6fc30c1ad03485ef707140b67623b95498d0d ]
+
@@ -22 +23,0 @@
-Cc: stable at dpdk.org
@@ -30 +31 @@
-index 20776919c2..f081921ffc 100644
+index 6ed00f722e..bd3a060963 100644
@@ -33,9 +34 @@
-@@ -1643,4 +1643,7 @@ dseg_done:
- * @param loc
- * Pointer to burst routine local context.
-+ * @param elts
-+ * Number of free elements in elts buffer to be checked, for zero
-+ * value the check is optimized out by compiler.
- * @param olx
- * Configured Tx offloads mask. It is fully defined at
-@@ -1656,4 +1659,5 @@ static __rte_always_inline enum mlx5_txcmp_code
+@@ -1623,4 +1623,5 @@ static __rte_always_inline enum mlx5_txcmp_code
@@ -47 +40 @@
-@@ -1670,5 +1674,5 @@ mlx5_tx_schedule_send(struct mlx5_txq_data *restrict txq,
+@@ -1637,5 +1638,5 @@ mlx5_tx_schedule_send(struct mlx5_txq_data *restrict txq,
@@ -54 +47,9 @@
-@@ -1736,9 +1740,10 @@ mlx5_tx_packet_multi_tso(struct mlx5_txq_data *__rte_restrict txq,
+@@ -1667,4 +1668,7 @@ mlx5_tx_schedule_send(struct mlx5_txq_data *restrict txq,
+ * @param loc
+ * Pointer to burst routine local context.
++ * @param elts
++ * Number of free elements in elts buffer to be checked, for zero
++ * value the check is optimized out by compiler.
+ * @param olx
+ * Configured Tx offloads mask. It is fully defined at
+@@ -1684,9 +1688,10 @@ mlx5_tx_packet_multi_tso(struct mlx5_txq_data *__rte_restrict txq,
@@ -66 +67 @@
-@@ -1834,9 +1839,10 @@ mlx5_tx_packet_multi_send(struct mlx5_txq_data *__rte_restrict txq,
+@@ -1782,9 +1787,10 @@ mlx5_tx_packet_multi_send(struct mlx5_txq_data *__rte_restrict txq,
@@ -78 +79 @@
-@@ -1949,14 +1955,5 @@ mlx5_tx_packet_multi_inline(struct mlx5_txq_data *__rte_restrict txq,
+@@ -1897,14 +1903,5 @@ mlx5_tx_packet_multi_inline(struct mlx5_txq_data *__rte_restrict txq,
@@ -94 +95 @@
-@@ -2064,4 +2061,14 @@ do_align:
+@@ -2012,4 +2009,14 @@ do_align:
@@ -109 +110 @@
-@@ -2224,5 +2231,5 @@ mlx5_tx_burst_tso(struct mlx5_txq_data *__rte_restrict txq,
+@@ -2172,5 +2179,5 @@ mlx5_tx_burst_tso(struct mlx5_txq_data *__rte_restrict txq,
@@ -116 +117 @@
-@@ -2602,14 +2609,4 @@ mlx5_tx_burst_empw_simple(struct mlx5_txq_data *__rte_restrict txq,
+@@ -2550,14 +2557,4 @@ mlx5_tx_burst_empw_simple(struct mlx5_txq_data *__rte_restrict txq,
@@ -131 +132 @@
-@@ -2622,4 +2619,14 @@ next_empw:
+@@ -2570,4 +2567,14 @@ next_empw:
@@ -146 +147 @@
-@@ -2776,14 +2783,4 @@ mlx5_tx_burst_empw_inline(struct mlx5_txq_data *__rte_restrict txq,
+@@ -2724,14 +2731,4 @@ mlx5_tx_burst_empw_inline(struct mlx5_txq_data *__rte_restrict txq,
@@ -161 +162 @@
-@@ -2793,4 +2790,14 @@ mlx5_tx_burst_empw_inline(struct mlx5_txq_data *__rte_restrict txq,
+@@ -2741,4 +2738,14 @@ mlx5_tx_burst_empw_inline(struct mlx5_txq_data *__rte_restrict txq,
@@ -176 +177 @@
-@@ -3075,9 +3082,10 @@ mlx5_tx_burst_single_send(struct mlx5_txq_data *__rte_restrict txq,
+@@ -3023,9 +3030,10 @@ mlx5_tx_burst_single_send(struct mlx5_txq_data *__rte_restrict txq,
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