patch 'common/cnxk: fix second pass flow rule layer type' has been queued to stable release 22.11.2
Xueming Li
xuemingl at nvidia.com
Sun Apr 9 17:23:09 CEST 2023
Hi,
FYI, your patch has been queued to stable release 22.11.2
Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 04/11/23. So please
shout if anyone has objections.
Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.
Queued patches are on a temporary branch at:
https://git.dpdk.org/dpdk-stable/log/?h=22.11-staging
This queued commit can be viewed at:
https://git.dpdk.org/dpdk-stable/log/?h=22.11-staging/commit/4dc4547f2df57baae38b12246f5a0a732fbdd3ff
Thanks.
Xueming Li <xuemingl at nvidia.com>
---
>From 4dc4547f2df57baae38b12246f5a0a732fbdd3ff Mon Sep 17 00:00:00 2001
From: Satheesh Paul <psatheesh at marvell.com>
Date: Mon, 27 Feb 2023 15:07:17 +0530
Subject: [PATCH] common/cnxk: fix second pass flow rule layer type
Cc: Xueming Li <xuemingl at nvidia.com>
When installing flow rule for second pass packets, set the
LA LTYPE to LA_CPT_HDR.
Fixes: 4968b362b639 ("common/cnxk: support CPT second pass flow rules")
Cc: stable at dpdk.org
[ upstream commit a0c837ad1fb5b6a8b10a284ffeb5f9e31bd8ff00 ]
Signed-off-by: Satheesh Paul <psatheesh at marvell.com>
---
drivers/common/cnxk/roc_npc_mcam.c | 39 +++++++++++++++++++++----
drivers/common/cnxk/roc_npc_mcam_dump.c | 6 ++--
drivers/common/cnxk/roc_npc_parse.c | 1 +
drivers/common/cnxk/roc_npc_priv.h | 1 +
4 files changed, 39 insertions(+), 8 deletions(-)
diff --git a/drivers/common/cnxk/roc_npc_mcam.c b/drivers/common/cnxk/roc_npc_mcam.c
index ceb0a733f0..3bf35cdf48 100644
--- a/drivers/common/cnxk/roc_npc_mcam.c
+++ b/drivers/common/cnxk/roc_npc_mcam.c
@@ -551,6 +551,8 @@ npc_mcam_alloc_and_write(struct npc *npc, struct roc_npc_flow *flow,
struct idev_cfg *idev;
uint16_t pf_func = 0;
uint16_t ctr = ~(0);
+ uint32_t la_offset;
+ uint64_t mask;
int rc, idx;
int entry;
@@ -617,17 +619,42 @@ npc_mcam_alloc_and_write(struct npc *npc, struct roc_npc_flow *flow,
flow->npc_action &= ~(GENMASK(19, 4));
flow->npc_action |= (uint64_t)pf_func << 4;
- npc_mcam_set_channel(flow, req, inl_dev->channel,
- inl_dev->chan_mask, false);
+ npc_mcam_set_channel(flow, req, inl_dev->channel, inl_dev->chan_mask,
+ false);
} else if (npc->is_sdp_link) {
- npc_mcam_set_channel(flow, req, npc->sdp_channel,
- npc->sdp_channel_mask,
+ npc_mcam_set_channel(flow, req, npc->sdp_channel, npc->sdp_channel_mask,
pst->is_second_pass_rule);
} else {
- npc_mcam_set_channel(flow, req, npc->channel,
- (BIT_ULL(12) - 1),
+ npc_mcam_set_channel(flow, req, npc->channel, (BIT_ULL(12) - 1),
pst->is_second_pass_rule);
}
+ /*
+ * For second pass rule, set LA LTYPE to CPT_HDR.
+ * For all other rules, set LA LTYPE to match both 1st pass and 2nd pass ltypes.
+ */
+ if (pst->is_second_pass_rule || (!pst->is_second_pass_rule && pst->has_eth_type)) {
+ la_offset = __builtin_popcount(npc->keyx_supp_nmask[flow->nix_intf] &
+ ((1ULL << 9 /* LA offset */) - 1));
+ la_offset *= 4;
+
+ mask = ~((0xfULL << la_offset));
+ req->entry_data.kw[0] &= mask;
+ req->entry_data.kw_mask[0] &= mask;
+ flow->mcam_data[0] &= mask;
+ flow->mcam_mask[0] &= mask;
+ if (pst->is_second_pass_rule) {
+ req->entry_data.kw[0] |= ((uint64_t)NPC_LT_LA_CPT_HDR) << la_offset;
+ req->entry_data.kw_mask[0] |= (0xFULL << la_offset);
+ flow->mcam_data[0] |= ((uint64_t)NPC_LT_LA_CPT_HDR) << la_offset;
+ flow->mcam_mask[0] |= (0xFULL << la_offset);
+ } else {
+ /* Mask ltype ETHER (0x2) and CPT_HDR (0xa) */
+ req->entry_data.kw[0] |= (0x2ULL << la_offset);
+ req->entry_data.kw_mask[0] |= (0x7ULL << la_offset);
+ flow->mcam_data[0] |= (0x2ULL << la_offset);
+ flow->mcam_mask[0] |= (0x7ULL << la_offset);
+ }
+ }
} else {
uint16_t pf_func = (flow->npc_action >> 4) & 0xffff;
diff --git a/drivers/common/cnxk/roc_npc_mcam_dump.c b/drivers/common/cnxk/roc_npc_mcam_dump.c
index fe57811a84..cc1599ef33 100644
--- a/drivers/common/cnxk/roc_npc_mcam_dump.c
+++ b/drivers/common/cnxk/roc_npc_mcam_dump.c
@@ -69,8 +69,10 @@ static const char *const ltype_str[NPC_MAX_LID][NPC_MAX_LT] = {
[NPC_LID_LA][NPC_LT_LA_IH_NIX_ETHER] = "LA_IH_NIX_ETHER",
[NPC_LID_LA][NPC_LT_LA_HIGIG2_ETHER] = "LA_HIGIG2_ETHER",
[NPC_LID_LA][NPC_LT_LA_IH_NIX_HIGIG2_ETHER] = "LA_IH_NIX_HIGIG2_ETHER",
- [NPC_LID_LA][NPC_LT_LA_CUSTOM_PRE_L2_ETHER] =
- "NPC_LT_LA_CUSTOM_PRE_L2_ETHER",
+ [NPC_LID_LA][NPC_LT_LA_CUSTOM_L2_90B_ETHER] = "LA_CUSTOM_L2_90B_ETHER",
+ [NPC_LID_LA][NPC_LT_LA_CPT_HDR] = "LA_CPT_HDR",
+ [NPC_LID_LA][NPC_LT_LA_CUSTOM_L2_24B_ETHER] = "LA_CUSTOM_L2_24B_ETHER",
+ [NPC_LID_LA][NPC_LT_LA_CUSTOM_PRE_L2_ETHER] = "NPC_LT_LA_CUSTOM_PRE_L2_ETHER",
[NPC_LID_LB][0] = "NONE",
[NPC_LID_LB][NPC_LT_LB_CTAG] = "LB_CTAG",
[NPC_LID_LB][NPC_LT_LB_STAG_QINQ] = "LB_STAG_QINQ",
diff --git a/drivers/common/cnxk/roc_npc_parse.c b/drivers/common/cnxk/roc_npc_parse.c
index 670f920117..b92970e69b 100644
--- a/drivers/common/cnxk/roc_npc_parse.c
+++ b/drivers/common/cnxk/roc_npc_parse.c
@@ -193,6 +193,7 @@ npc_parse_la(struct npc_parse_state *pst)
if (pst->pattern->type != ROC_NPC_ITEM_TYPE_ETH)
return 0;
+ pst->has_eth_type = true;
eth_item = pst->pattern->spec;
lid = NPC_LID_LA;
diff --git a/drivers/common/cnxk/roc_npc_priv.h b/drivers/common/cnxk/roc_npc_priv.h
index f034f72a04..1de33932e7 100644
--- a/drivers/common/cnxk/roc_npc_priv.h
+++ b/drivers/common/cnxk/roc_npc_priv.h
@@ -199,6 +199,7 @@ struct npc_parse_state {
bool set_vlan_ltype_mask;
bool set_ipv6ext_ltype_mask;
bool is_second_pass_rule;
+ bool has_eth_type;
};
enum npc_kpu_parser_flag {
--
2.25.1
---
Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- - 2023-04-09 21:45:38.882702000 +0800
+++ 0001-common-cnxk-fix-second-pass-flow-rule-layer-type.patch 2023-04-09 21:45:38.569042200 +0800
@@ -1 +1 @@
-From a0c837ad1fb5b6a8b10a284ffeb5f9e31bd8ff00 Mon Sep 17 00:00:00 2001
+From 4dc4547f2df57baae38b12246f5a0a732fbdd3ff Mon Sep 17 00:00:00 2001
@@ -3 +3 @@
-Date: Tue, 31 Jan 2023 09:06:52 +0530
+Date: Mon, 27 Feb 2023 15:07:17 +0530
@@ -4,0 +5 @@
+Cc: Xueming Li <xuemingl at nvidia.com>
@@ -11,0 +13,2 @@
+[ upstream commit a0c837ad1fb5b6a8b10a284ffeb5f9e31bd8ff00 ]
+
@@ -13 +15,0 @@
-Reviewed-by: Kiran Kumar K <kirankumark at marvell.com>
@@ -15,3 +17,5 @@
- drivers/common/cnxk/roc_npc_mcam.c | 24 +++++++++++++++++-------
- drivers/common/cnxk/roc_npc_mcam_dump.c | 6 ++++--
- 2 files changed, 21 insertions(+), 9 deletions(-)
+ drivers/common/cnxk/roc_npc_mcam.c | 39 +++++++++++++++++++++----
+ drivers/common/cnxk/roc_npc_mcam_dump.c | 6 ++--
+ drivers/common/cnxk/roc_npc_parse.c | 1 +
+ drivers/common/cnxk/roc_npc_priv.h | 1 +
+ 4 files changed, 39 insertions(+), 8 deletions(-)
@@ -20 +24 @@
-index 312424d1c2..06f3212e8d 100644
+index ceb0a733f0..3bf35cdf48 100644
@@ -23,2 +27,26 @@
-@@ -668,22 +668,32 @@ npc_mcam_alloc_and_write(struct npc *npc, struct roc_npc_flow *flow,
- npc_mcam_set_channel(flow, req, npc->channel, (BIT_ULL(12) - 1),
+@@ -551,6 +551,8 @@ npc_mcam_alloc_and_write(struct npc *npc, struct roc_npc_flow *flow,
+ struct idev_cfg *idev;
+ uint16_t pf_func = 0;
+ uint16_t ctr = ~(0);
++ uint32_t la_offset;
++ uint64_t mask;
+ int rc, idx;
+ int entry;
+
+@@ -617,17 +619,42 @@ npc_mcam_alloc_and_write(struct npc *npc, struct roc_npc_flow *flow,
+ flow->npc_action &= ~(GENMASK(19, 4));
+ flow->npc_action |= (uint64_t)pf_func << 4;
+
+- npc_mcam_set_channel(flow, req, inl_dev->channel,
+- inl_dev->chan_mask, false);
++ npc_mcam_set_channel(flow, req, inl_dev->channel, inl_dev->chan_mask,
++ false);
+ } else if (npc->is_sdp_link) {
+- npc_mcam_set_channel(flow, req, npc->sdp_channel,
+- npc->sdp_channel_mask,
++ npc_mcam_set_channel(flow, req, npc->sdp_channel, npc->sdp_channel_mask,
+ pst->is_second_pass_rule);
+ } else {
+- npc_mcam_set_channel(flow, req, npc->channel,
+- (BIT_ULL(12) - 1),
++ npc_mcam_set_channel(flow, req, npc->channel, (BIT_ULL(12) - 1),
@@ -27,2 +54,0 @@
-- /* Always match both 1st pass and 2nd pass ltypes for all rules */
-- if (!pst->is_second_pass_rule && pst->has_eth_type) {
@@ -34,14 +60,9 @@
- la_offset = __builtin_popcount(npc->keyx_supp_nmask[flow->nix_intf] &
- ((1ULL << 9 /* LA offset */) - 1));
- la_offset *= 4;
-
- mask = ~((0xfULL << la_offset));
-- /* Mask ltype ETHER (0x2) and CPT_HDR (0xa) */
- req->entry_data.kw[0] &= mask;
- req->entry_data.kw_mask[0] &= mask;
-- req->entry_data.kw[0] |= (0x2ULL << la_offset);
-- req->entry_data.kw_mask[0] |= (0x7ULL << la_offset);
- flow->mcam_data[0] &= mask;
- flow->mcam_mask[0] &= mask;
-- flow->mcam_data[0] |= (0x2ULL << la_offset);
-- flow->mcam_mask[0] |= (0x7ULL << la_offset);
++ la_offset = __builtin_popcount(npc->keyx_supp_nmask[flow->nix_intf] &
++ ((1ULL << 9 /* LA offset */) - 1));
++ la_offset *= 4;
++
++ mask = ~((0xfULL << la_offset));
++ req->entry_data.kw[0] &= mask;
++ req->entry_data.kw_mask[0] &= mask;
++ flow->mcam_data[0] &= mask;
++ flow->mcam_mask[0] &= mask;
@@ -60 +81 @@
- }
++ }
@@ -62,0 +84 @@
+
@@ -64 +86 @@
-index 2aaa2ac671..40909b45e6 100644
+index fe57811a84..cc1599ef33 100644
@@ -79,0 +102,24 @@
+diff --git a/drivers/common/cnxk/roc_npc_parse.c b/drivers/common/cnxk/roc_npc_parse.c
+index 670f920117..b92970e69b 100644
+--- a/drivers/common/cnxk/roc_npc_parse.c
++++ b/drivers/common/cnxk/roc_npc_parse.c
+@@ -193,6 +193,7 @@ npc_parse_la(struct npc_parse_state *pst)
+ if (pst->pattern->type != ROC_NPC_ITEM_TYPE_ETH)
+ return 0;
+
++ pst->has_eth_type = true;
+ eth_item = pst->pattern->spec;
+
+ lid = NPC_LID_LA;
+diff --git a/drivers/common/cnxk/roc_npc_priv.h b/drivers/common/cnxk/roc_npc_priv.h
+index f034f72a04..1de33932e7 100644
+--- a/drivers/common/cnxk/roc_npc_priv.h
++++ b/drivers/common/cnxk/roc_npc_priv.h
+@@ -199,6 +199,7 @@ struct npc_parse_state {
+ bool set_vlan_ltype_mask;
+ bool set_ipv6ext_ltype_mask;
+ bool is_second_pass_rule;
++ bool has_eth_type;
+ };
+
+ enum npc_kpu_parser_flag {
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