patch 'net/mlx5: reduce counter pool name length' has been queued to stable release 22.11.3

Xueming Li xuemingl at nvidia.com
Thu Aug 10 01:59:00 CEST 2023


Hi,

FYI, your patch has been queued to stable release 22.11.3

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 08/11/23. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Queued patches are on a temporary branch at:
https://git.dpdk.org/dpdk-stable/log/?h=22.11-staging

This queued commit can be viewed at:
https://git.dpdk.org/dpdk-stable/commit/?h=22.11-staging&id=cdd4d9bca6dbb570c6286c46a7ca133259c02af1

Thanks.

Xueming Li <xuemingl at nvidia.com>

---
>From cdd4d9bca6dbb570c6286c46a7ca133259c02af1 Mon Sep 17 00:00:00 2001
From: Bing Zhao <bingz at nvidia.com>
Date: Fri, 30 Jun 2023 15:57:30 +0300
Subject: [PATCH] net/mlx5: reduce counter pool name length
Cc: Xueming Li <xuemingl at nvidia.com>

[ upstream commit 1c955e4cf72287940c180c31e14ccfd1f90dac0f ]

The name size of a rte_ring is RTE_MEMZONE_NAMESIZE with the value 32
by default. When creating a HWS counter pool cache, the final string
format was "RG_MLX5_HWS_CNT_POOL_%u_cache/%u" and it could support
less than 1000 variants. For example, if the first %u representing
port id is 100 and it will take all the available characters then the
second %u for queues will be discarded. If there was more than one
rule creation queue, the rte_ring could not be created.

By reducing the fixed character number and using hexadecimal format,
the issue can be overcome with an assumption that not all the integer
fields for queue index is used.

Fixes: 13ea6bdcc7ee ("net/mlx5: support counters in cross port shared mode")
Fixes: 4d368e1da3a4 ("net/mlx5: support flow counter action for HWS")

Signed-off-by: Bing Zhao <bingz at nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo at nvidia.com>
---
 drivers/net/mlx5/mlx5_hws_cnt.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/net/mlx5/mlx5_hws_cnt.c b/drivers/net/mlx5/mlx5_hws_cnt.c
index 51704ef754..8ccc6ab1f8 100644
--- a/drivers/net/mlx5/mlx5_hws_cnt.c
+++ b/drivers/net/mlx5/mlx5_hws_cnt.c
@@ -410,8 +410,7 @@ mlx5_hws_cnt_pool_init(struct mlx5_dev_ctx_shared *sh,
 		goto error;
 	}
 	for (qidx = 0; qidx < ccfg->q_num; qidx++) {
-		snprintf(mz_name, sizeof(mz_name), "%s_cache/%u", pcfg->name,
-				qidx);
+		snprintf(mz_name, sizeof(mz_name), "%s_qc/%x", pcfg->name, qidx);
 		cntp->cache->qcache[qidx] = rte_ring_create(mz_name, ccfg->size,
 				SOCKET_ID_ANY,
 				RING_F_SP_ENQ | RING_F_SC_DEQ |
@@ -634,7 +633,7 @@ mlx5_hws_cnt_pool_create(struct rte_eth_dev *dev,
 			SOCKET_ID_ANY);
 	if (mp_name == NULL)
 		goto error;
-	snprintf(mp_name, RTE_MEMZONE_NAMESIZE, "MLX5_HWS_CNT_POOL_%u",
+	snprintf(mp_name, RTE_MEMZONE_NAMESIZE, "MLX5_HWS_CNT_P_%x",
 			dev->data->port_id);
 	pcfg.name = mp_name;
 	pcfg.request_num = pattr->nb_counters;
-- 
2.25.1

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2023-08-09 21:51:20.280864400 +0800
+++ 0081-net-mlx5-reduce-counter-pool-name-length.patch	2023-08-09 21:51:18.244352000 +0800
@@ -1 +1 @@
-From 1c955e4cf72287940c180c31e14ccfd1f90dac0f Mon Sep 17 00:00:00 2001
+From cdd4d9bca6dbb570c6286c46a7ca133259c02af1 Mon Sep 17 00:00:00 2001
@@ -4,0 +5,3 @@
+Cc: Xueming Li <xuemingl at nvidia.com>
+
+[ upstream commit 1c955e4cf72287940c180c31e14ccfd1f90dac0f ]
@@ -20 +22,0 @@
-Cc: stable at dpdk.org
@@ -25,2 +27,2 @@
- drivers/net/mlx5/mlx5_hws_cnt.c | 9 +++------
- 1 file changed, 3 insertions(+), 6 deletions(-)
+ drivers/net/mlx5/mlx5_hws_cnt.c | 5 ++---
+ 1 file changed, 2 insertions(+), 3 deletions(-)
@@ -29 +31 @@
-index d98df68f39..18d80f34ba 100644
+index 51704ef754..8ccc6ab1f8 100644
@@ -32 +34 @@
-@@ -419,8 +419,7 @@ mlx5_hws_cnt_pool_init(struct mlx5_dev_ctx_shared *sh,
+@@ -410,8 +410,7 @@ mlx5_hws_cnt_pool_init(struct mlx5_dev_ctx_shared *sh,
@@ -42,7 +44,2 @@
-@@ -612,12 +611,10 @@ mlx5_hws_cnt_pool_create(struct rte_eth_dev *dev,
- 	int ret = 0;
- 	size_t sz;
- 
--	mp_name = mlx5_malloc(MLX5_MEM_ZERO, RTE_MEMZONE_NAMESIZE, 0,
--			SOCKET_ID_ANY);
-+	mp_name = mlx5_malloc(MLX5_MEM_ZERO, RTE_MEMZONE_NAMESIZE, 0, SOCKET_ID_ANY);
+@@ -634,7 +633,7 @@ mlx5_hws_cnt_pool_create(struct rte_eth_dev *dev,
+ 			SOCKET_ID_ANY);
@@ -52,2 +49,2 @@
--			dev->data->port_id);
-+	snprintf(mp_name, RTE_MEMZONE_NAMESIZE, "MLX5_HWS_CNT_P_%x", dev->data->port_id);
++	snprintf(mp_name, RTE_MEMZONE_NAMESIZE, "MLX5_HWS_CNT_P_%x",
+ 			dev->data->port_id);
@@ -56 +52,0 @@
- 	pcfg.alloc_factor = HWS_CNT_ALLOC_FACTOR_DEFAULT;


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