patch 'net/hns3: fix IMP or global reset' has been queued to stable release 22.11.4
Xueming Li
xuemingl at nvidia.com
Mon Dec 11 11:10:49 CET 2023
Hi,
FYI, your patch has been queued to stable release 22.11.4
Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 12/13/23. So please
shout if anyone has objections.
Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.
Queued patches are on a temporary branch at:
https://git.dpdk.org/dpdk-stable/log/?h=22.11-staging
This queued commit can be viewed at:
https://git.dpdk.org/dpdk-stable/commit/?h=22.11-staging&id=9a62d06e64ab1c7708c2197d23f198eb3daaccce
Thanks.
Xueming Li <xuemingl at nvidia.com>
---
>From 9a62d06e64ab1c7708c2197d23f198eb3daaccce Mon Sep 17 00:00:00 2001
From: Dengdui Huang <huangdengdui at huawei.com>
Date: Fri, 27 Oct 2023 14:09:45 +0800
Subject: [PATCH] net/hns3: fix IMP or global reset
Cc: Xueming Li <xuemingl at nvidia.com>
[ upstream commit 1eee1ea75c0eadaea6dde368b289cf0acf6a1190 ]
Currently, when the IMP or Global reset detected, the vector0
interrupt is enabled before the reset process is completed.
At this moment, if the initialization of IMP is not completed,
and the vector0 interrupt may continue to be reported. In this
scenario, the IMP/global reset being performed by the driver
does not need to be interrupted. Therefore, for IMP and global
resets, the driver has to enable the interrupt after the end
of reset.
The RAS interrupt is also shared with the vector0 interrupt.
When the interrupt is disabled, the RAS interrupt can still be
reported to the driver and the driver interrupt processing
function is also called. In this case, the interrupt status of
the IMP/global may still exist. Therefore, this patch also has
to the check of the new reset level based on the priority of
reset level in the interrupt handler.
Fixes: 2790c6464725 ("net/hns3: support device reset")
Fixes: 3988ab0eee52 ("net/hns3: add abnormal interrupt process")
Signed-off-by: Dengdui Huang <huangdengdui at huawei.com>
---
drivers/net/hns3/hns3_ethdev.c | 88 ++++++++++++++++++++++++++++------
drivers/net/hns3/hns3_ethdev.h | 1 +
drivers/net/hns3/hns3_intr.c | 2 +
3 files changed, 77 insertions(+), 14 deletions(-)
diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c
index 576cc56216..036062947d 100644
--- a/drivers/net/hns3/hns3_ethdev.c
+++ b/drivers/net/hns3/hns3_ethdev.c
@@ -219,6 +219,30 @@ out:
return ret;
}
+void
+hns3_clear_reset_event(struct hns3_hw *hw)
+{
+ uint32_t clearval = 0;
+
+ switch (hw->reset.level) {
+ case HNS3_IMP_RESET:
+ clearval = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
+ break;
+ case HNS3_GLOBAL_RESET:
+ clearval = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
+ break;
+ default:
+ break;
+ }
+
+ if (clearval == 0)
+ return;
+
+ hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, clearval);
+
+ hns3_pf_enable_irq0(hw);
+}
+
static void
hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
{
@@ -291,6 +315,34 @@ hns3_delay_before_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uin
}
}
+static bool
+hns3_reset_event_valid(struct hns3_hw *hw)
+{
+ struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
+ enum hns3_reset_level new_req = HNS3_NONE_RESET;
+ enum hns3_reset_level last_req;
+ uint32_t vector0_int;
+
+ vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
+ if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int)
+ new_req = HNS3_IMP_RESET;
+ else if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int)
+ new_req = HNS3_GLOBAL_RESET;
+ if (new_req == HNS3_NONE_RESET)
+ return true;
+
+ last_req = hns3_get_reset_level(hns, &hw->reset.pending);
+ if (last_req == HNS3_NONE_RESET)
+ return true;
+
+ if (new_req > last_req)
+ return true;
+
+ hns3_warn(hw, "last_req (%u) less than or equal to new_req (%u) ignore",
+ last_req, new_req);
+ return false;
+}
+
static void
hns3_interrupt_handler(void *param)
{
@@ -303,6 +355,9 @@ hns3_interrupt_handler(void *param)
uint32_t ras_int;
uint32_t cmdq_int;
+ if (!hns3_reset_event_valid(hw))
+ return;
+
/* Disable interrupt */
hns3_pf_disable_irq0(hw);
@@ -331,7 +386,11 @@ hns3_interrupt_handler(void *param)
}
/* Enable interrupt if it is not cause by reset */
- hns3_pf_enable_irq0(hw);
+ if (event_cause == HNS3_VECTOR0_EVENT_ERR ||
+ event_cause == HNS3_VECTOR0_EVENT_MBX ||
+ event_cause == HNS3_VECTOR0_EVENT_PTP ||
+ event_cause == HNS3_VECTOR0_EVENT_OTHER)
+ hns3_pf_enable_irq0(hw);
}
static int
@@ -5523,7 +5582,7 @@ is_pf_reset_done(struct hns3_hw *hw)
return true;
}
-static void
+static enum hns3_reset_level
hns3_detect_reset_event(struct hns3_hw *hw)
{
struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
@@ -5535,11 +5594,9 @@ hns3_detect_reset_event(struct hns3_hw *hw)
vector0_intr_state = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_intr_state) {
__atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
- hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
new_req = HNS3_IMP_RESET;
} else if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_intr_state) {
__atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
- hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
new_req = HNS3_GLOBAL_RESET;
}
@@ -5547,13 +5604,16 @@ hns3_detect_reset_event(struct hns3_hw *hw)
hns3_schedule_delayed_reset(hns);
hns3_warn(hw, "High level reset detected, delay do reset");
}
+
+ return new_req;
}
bool
hns3_is_reset_pending(struct hns3_adapter *hns)
{
+ enum hns3_reset_level new_req;
struct hns3_hw *hw = &hns->hw;
- enum hns3_reset_level reset;
+ enum hns3_reset_level last_req;
/*
* Only primary can process can process the reset event,
@@ -5562,17 +5622,17 @@ hns3_is_reset_pending(struct hns3_adapter *hns)
if (rte_eal_process_type() != RTE_PROC_PRIMARY)
return false;
- hns3_detect_reset_event(hw);
- reset = hns3_get_reset_level(hns, &hw->reset.pending);
- if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&
- hw->reset.level < reset) {
- hns3_warn(hw, "High level reset %d is pending", reset);
+ new_req = hns3_detect_reset_event(hw);
+ last_req = hns3_get_reset_level(hns, &hw->reset.pending);
+ if (last_req != HNS3_NONE_RESET && new_req != HNS3_NONE_RESET &&
+ new_req < last_req) {
+ hns3_warn(hw, "High level reset %d is pending", last_req);
return true;
}
- reset = hns3_get_reset_level(hns, &hw->reset.request);
- if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&
- hw->reset.level < reset) {
- hns3_warn(hw, "High level reset %d is request", reset);
+ last_req = hns3_get_reset_level(hns, &hw->reset.request);
+ if (last_req != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&
+ hw->reset.level < last_req) {
+ hns3_warn(hw, "High level reset %d is request", last_req);
return true;
}
return false;
diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h
index 58572948fe..f86512bd35 100644
--- a/drivers/net/hns3/hns3_ethdev.h
+++ b/drivers/net/hns3/hns3_ethdev.h
@@ -1029,6 +1029,7 @@ void hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query);
void hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status,
uint32_t link_speed, uint8_t link_duplex);
void hns3vf_update_push_lsc_cap(struct hns3_hw *hw, bool supported);
+void hns3_clear_reset_event(struct hns3_hw *hw);
static inline bool
diff --git a/drivers/net/hns3/hns3_intr.c b/drivers/net/hns3/hns3_intr.c
index baf5f58e9e..c5a3e3797c 100644
--- a/drivers/net/hns3/hns3_intr.c
+++ b/drivers/net/hns3/hns3_intr.c
@@ -2749,6 +2749,7 @@ hns3_reset_post(struct hns3_adapter *hns)
/* IMP will wait ready flag before reset */
hns3_notify_reset_ready(hw, false);
hns3_clear_reset_level(hw, &hw->reset.pending);
+ hns3_clear_reset_event(hw);
__atomic_store_n(&hns->hw.reset.resetting, 0, __ATOMIC_RELAXED);
hw->reset.attempts = 0;
hw->reset.stats.success_cnt++;
@@ -2798,6 +2799,7 @@ hns3_reset_fail_handle(struct hns3_adapter *hns)
struct timeval tv;
hns3_clear_reset_level(hw, &hw->reset.pending);
+ hns3_clear_reset_event(hw);
if (hns3_reset_err_handle(hns)) {
hw->reset.stage = RESET_STAGE_PREWAIT;
hns3_schedule_reset(hns);
--
2.25.1
---
Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- - 2023-12-11 17:56:23.963748300 +0800
+++ 0024-net-hns3-fix-IMP-or-global-reset.patch 2023-12-11 17:56:22.927652300 +0800
@@ -1 +1 @@
-From 1eee1ea75c0eadaea6dde368b289cf0acf6a1190 Mon Sep 17 00:00:00 2001
+From 9a62d06e64ab1c7708c2197d23f198eb3daaccce Mon Sep 17 00:00:00 2001
@@ -4,0 +5,3 @@
+Cc: Xueming Li <xuemingl at nvidia.com>
+
+[ upstream commit 1eee1ea75c0eadaea6dde368b289cf0acf6a1190 ]
@@ -25 +27,0 @@
-Cc: stable at dpdk.org
@@ -35 +37 @@
-index 18afc0fa0a..bb9dde9c5b 100644
+index 576cc56216..036062947d 100644
@@ -38 +40 @@
-@@ -215,6 +215,30 @@ out:
+@@ -219,6 +219,30 @@ out:
@@ -69 +71 @@
-@@ -287,6 +311,34 @@ hns3_delay_before_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uin
+@@ -291,6 +315,34 @@ hns3_delay_before_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uin
@@ -104 +106 @@
-@@ -299,6 +351,9 @@ hns3_interrupt_handler(void *param)
+@@ -303,6 +355,9 @@ hns3_interrupt_handler(void *param)
@@ -114 +116 @@
-@@ -327,7 +382,11 @@ hns3_interrupt_handler(void *param)
+@@ -331,7 +386,11 @@ hns3_interrupt_handler(void *param)
@@ -127 +129 @@
-@@ -5489,7 +5548,7 @@ is_pf_reset_done(struct hns3_hw *hw)
+@@ -5523,7 +5582,7 @@ is_pf_reset_done(struct hns3_hw *hw)
@@ -136 +138 @@
-@@ -5501,11 +5560,9 @@ hns3_detect_reset_event(struct hns3_hw *hw)
+@@ -5535,11 +5594,9 @@ hns3_detect_reset_event(struct hns3_hw *hw)
@@ -148 +150 @@
-@@ -5513,13 +5570,16 @@ hns3_detect_reset_event(struct hns3_hw *hw)
+@@ -5547,13 +5604,16 @@ hns3_detect_reset_event(struct hns3_hw *hw)
@@ -166 +168 @@
-@@ -5528,17 +5588,17 @@ hns3_is_reset_pending(struct hns3_adapter *hns)
+@@ -5562,17 +5622,17 @@ hns3_is_reset_pending(struct hns3_adapter *hns)
@@ -194 +196 @@
-index c85a6912ad..0e8d043704 100644
+index 58572948fe..f86512bd35 100644
@@ -197 +199 @@
-@@ -1033,6 +1033,7 @@ void hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query);
+@@ -1029,6 +1029,7 @@ void hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query);
@@ -203 +204,0 @@
- const char *hns3_get_media_type_name(uint8_t media_type);
@@ -204,0 +206 @@
+ static inline bool
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