patch 'event/dlb2: fix disable PASID' has been queued to stable release 22.11.4

[Xueming Li]

Hi,

FYI, your patch has been queued to stable release 22.11.4

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 12/13/23. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Queued patches are on a temporary branch at:
https://git.dpdk.org/dpdk-stable/log/?h=22.11-staging

This queued commit can be viewed at:
https://git.dpdk.org/dpdk-stable/commit/?h=22.11-staging&id=6c688dec84856bd68682f8f6b082b11868906132

Thanks.

Xueming Li <xuemingl at nvidia.com>

---
>From 6c688dec84856bd68682f8f6b082b11868906132 Mon Sep 17 00:00:00 2001
From: Abdullah Sevincer <abdullah.sevincer at intel.com>
Date: Thu, 9 Nov 2023 13:45:44 -0600
Subject: [PATCH] event/dlb2: fix disable PASID
Cc: Xueming Li <xuemingl at nvidia.com>

[ upstream commit 5a6878335b8179337ec2d9931debf1f46525e8fc ]

In vfio-pci driver when PASID is enabled by default DLB hardware puts
DLB in SIOV mode. This breaks DLB PF-PMD mode. For DLB PF-PMD mode to
function properly PASID needs to be disabled.

In this commit this issue is addressed and PASID is disabled by writing
a zero to PASID control register.

Fixes: 5433956d5185 ("event/dlb2: add eventdev probe")

Signed-off-by: Abdullah Sevincer <abdullah.sevincer at intel.com>
---
 drivers/event/dlb2/pf/dlb2_main.c | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/drivers/event/dlb2/pf/dlb2_main.c b/drivers/event/dlb2/pf/dlb2_main.c
index 64a59f7616..12b65c3b98 100644
--- a/drivers/event/dlb2/pf/dlb2_main.c
+++ b/drivers/event/dlb2/pf/dlb2_main.c
@@ -47,6 +47,7 @@
 #define DLB2_PCI_CAP_ID_MSIX      0x11
 #define DLB2_PCI_EXT_CAP_ID_PRI   0x13
 #define DLB2_PCI_EXT_CAP_ID_ACS   0xD
+#define DLB2_PCI_EXT_CAP_ID_PASID 0x1B	/* Process Address Space ID */
 
 #define DLB2_PCI_PRI_CTRL_ENABLE         0x1
 #define DLB2_PCI_PRI_ALLOC_REQ           0xC
@@ -65,6 +66,8 @@
 #define DLB2_PCI_ACS_CR                  0x8
 #define DLB2_PCI_ACS_UF                  0x10
 #define DLB2_PCI_ACS_EC                  0x20
+#define DLB2_PCI_PASID_CTRL              0x06    /* PASID control register */
+#define DLB2_PCI_PASID_CAP_OFFSET        0x148   /* PASID capability offset */
 
 static int dlb2_pci_find_capability(struct rte_pci_device *pdev, uint32_t id)
 {
@@ -258,12 +261,14 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev)
 	uint16_t rt_ctl_word;
 	uint32_t pri_reqs_dword;
 	uint16_t pri_ctrl_word;
+	uint16_t pasid_ctrl;
 
 	int pcie_cap_offset;
 	int pri_cap_offset;
 	int msix_cap_offset;
 	int err_cap_offset;
 	int acs_cap_offset;
+	int pasid_cap_offset;
 	int wait_count;
 
 	uint16_t devsta_busy_word;
@@ -583,6 +588,28 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev)
 		}
 	}
 
+	/* The current Linux kernel vfio driver does not expose PASID capability to
+	 * users. It also enables PASID by default, which breaks DLB PF PMD. We have
+	 * to use the hardcoded offset for now to disable PASID.
+	 */
+	pasid_cap_offset = DLB2_PCI_PASID_CAP_OFFSET;
+
+	off = pasid_cap_offset + DLB2_PCI_PASID_CTRL;
+	if (rte_pci_read_config(pdev, &pasid_ctrl, 2, off) != 2)
+		pasid_ctrl = 0;
+
+	if (pasid_ctrl) {
+		DLB2_INFO(dlb2_dev, "DLB2 disabling pasid...\n");
+
+		pasid_ctrl = 0;
+		ret = rte_pci_write_config(pdev, &pasid_ctrl, 2, off);
+		if (ret != 2) {
+			DLB2_LOG_ERR("[%s()] failed to write the pcie config space at offset %d\n",
+				__func__, (int)off);
+			return ret;
+		}
+	}
+
 	/* Disable PASID if it is enabled by default, which
 	 * breaks the DLB if enabled.
 	 */
-- 
2.25.1

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2023-12-11 17:56:26.949730200 +0800
+++ 0121-event-dlb2-fix-disable-PASID.patch	2023-12-11 17:56:23.247652300 +0800
@@ -1 +1 @@
-From 5a6878335b8179337ec2d9931debf1f46525e8fc Mon Sep 17 00:00:00 2001
+From 6c688dec84856bd68682f8f6b082b11868906132 Mon Sep 17 00:00:00 2001
@@ -3,2 +3,5 @@
-Date: Mon, 6 Nov 2023 11:05:21 -0600
-Subject: [PATCH] event/dlb2: disable PASID
+Date: Thu, 9 Nov 2023 13:45:44 -0600
+Subject: [PATCH] event/dlb2: fix disable PASID
+Cc: Xueming Li <xuemingl at nvidia.com>
+
+[ upstream commit 5a6878335b8179337ec2d9931debf1f46525e8fc ]
@@ -14 +16,0 @@
-Cc: stable at dpdk.org
@@ -18,2 +20,2 @@
- drivers/event/dlb2/pf/dlb2_main.c | 11 +++++++++++
- 1 file changed, 11 insertions(+)
+ drivers/event/dlb2/pf/dlb2_main.c | 27 +++++++++++++++++++++++++++
+ 1 file changed, 27 insertions(+)
@@ -22 +24 @@
-index aa03e4c311..61a7b39eef 100644
+index 64a59f7616..12b65c3b98 100644
@@ -25,4 +27,13 @@
-@@ -26,6 +26,7 @@
- #define PF_ID_ZERO 0	/* PF ONLY! */
- #define NO_OWNER_VF 0	/* PF ONLY! */
- #define NOT_VF_REQ false /* PF ONLY! */
+@@ -47,6 +47,7 @@
+ #define DLB2_PCI_CAP_ID_MSIX      0x11
+ #define DLB2_PCI_EXT_CAP_ID_PRI   0x13
+ #define DLB2_PCI_EXT_CAP_ID_ACS   0xD
++#define DLB2_PCI_EXT_CAP_ID_PASID 0x1B	/* Process Address Space ID */
+ 
+ #define DLB2_PCI_PRI_CTRL_ENABLE         0x1
+ #define DLB2_PCI_PRI_ALLOC_REQ           0xC
+@@ -65,6 +66,8 @@
+ #define DLB2_PCI_ACS_CR                  0x8
+ #define DLB2_PCI_ACS_UF                  0x10
+ #define DLB2_PCI_ACS_EC                  0x20
++#define DLB2_PCI_PASID_CTRL              0x06    /* PASID control register */
@@ -31,3 +42,18 @@
- static int
- dlb2_pf_init_driver_state(struct dlb2_dev *dlb2_dev)
-@@ -514,6 +515,16 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev)
+ static int dlb2_pci_find_capability(struct rte_pci_device *pdev, uint32_t id)
+ {
+@@ -258,12 +261,14 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev)
+ 	uint16_t rt_ctl_word;
+ 	uint32_t pri_reqs_dword;
+ 	uint16_t pri_ctrl_word;
++	uint16_t pasid_ctrl;
+ 
+ 	int pcie_cap_offset;
+ 	int pri_cap_offset;
+ 	int msix_cap_offset;
+ 	int err_cap_offset;
+ 	int acs_cap_offset;
++	int pasid_cap_offset;
+ 	int wait_count;
+ 
+ 	uint16_t devsta_busy_word;
+@@ -583,6 +588,28 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev)
@@ -37,2 +63,3 @@
-+	/* Disable PASID if it is enabled by default, which
-+	 * breaks the DLB if enabled.
++	/* The current Linux kernel vfio driver does not expose PASID capability to
++	 * users. It also enables PASID by default, which breaks DLB PF PMD. We have
++	 * to use the hardcoded offset for now to disable PASID.
@@ -40,3 +67,13 @@
-+	off = DLB2_PCI_PASID_CAP_OFFSET + RTE_PCI_PASID_CTRL;
-+	if (rte_pci_pasid_set_state(pdev, off, false)) {
-+		DLB2_LOG_ERR("[%s()] failed to write the pcie config space at offset %d\n",
++	pasid_cap_offset = DLB2_PCI_PASID_CAP_OFFSET;
++
++	off = pasid_cap_offset + DLB2_PCI_PASID_CTRL;
++	if (rte_pci_read_config(pdev, &pasid_ctrl, 2, off) != 2)
++		pasid_ctrl = 0;
++
++	if (pasid_ctrl) {
++		DLB2_INFO(dlb2_dev, "DLB2 disabling pasid...\n");
++
++		pasid_ctrl = 0;
++		ret = rte_pci_write_config(pdev, &pasid_ctrl, 2, off);
++		if (ret != 2) {
++			DLB2_LOG_ERR("[%s()] failed to write the pcie config space at offset %d\n",
@@ -44 +81,2 @@
-+		return -1;
++			return ret;
++		}
@@ -47,3 +85,3 @@
- 	return 0;
- }
- 
+ 	/* Disable PASID if it is enabled by default, which
+ 	 * breaks the DLB if enabled.
+ 	 */