patch 'net/txgbe: fix default signal quality value for KX/KX4' has been queued to stable release 20.11.8

[luca.boccassi at gmail.com]

Hi,

FYI, your patch has been queued to stable release 20.11.8

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 02/25/23. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Queued patches are on a temporary branch at:
https://github.com/bluca/dpdk-stable

This queued commit can be viewed at:
https://github.com/bluca/dpdk-stable/commit/62b31a67404a62fd3e09149f17e541f7f03db80d

Thanks.

Luca Boccassi

---
>From 62b31a67404a62fd3e09149f17e541f7f03db80d Mon Sep 17 00:00:00 2001
From: Jiawen Wu <jiawenwu at trustnetic.com>
Date: Thu, 2 Feb 2023 17:21:25 +0800
Subject: [PATCH] net/txgbe: fix default signal quality value for KX/KX4

[ upstream commit 7211175417d4f6a7b03a0e7e7355dc62fced8512 ]

On old firmware versions, the default value of signal quality(TX_EQ) is
configured by the driver. Fix it for KX/KX4 mode.

Fixes: 01c3cf5c85a7 ("net/txgbe: add autoneg control read and write")

Signed-off-by: Jiawen Wu <jiawenwu at trustnetic.com>
---
 drivers/net/txgbe/base/txgbe_phy.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/net/txgbe/base/txgbe_phy.c b/drivers/net/txgbe/base/txgbe_phy.c
index ce6d580636..73f3cdced1 100644
--- a/drivers/net/txgbe/base/txgbe_phy.c
+++ b/drivers/net/txgbe/base/txgbe_phy.c
@@ -1491,9 +1491,10 @@ txgbe_set_link_to_kx4(struct txgbe_hw *hw, bool autoneg)
 	wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0x4F00);
 
 	value = (0x1804 & ~0x3F3F);
+	value |= 40 << 8;
 	wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
 
-	value = (0x50 & ~0x7F) | 40 | (1 << 6);
+	value = (0x50 & ~0x7F) | (1 << 6);
 	wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
 
 	for (i = 0; i < 4; i++) {
@@ -1701,10 +1702,10 @@ txgbe_set_link_to_kx(struct txgbe_hw *hw,
 
 	wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0x4F00);
 
-	value = (0x1804 & ~0x3F3F) | (24 << 8) | 4;
+	value = (0x1804 & ~0x3F3F) | (24 << 8);
 	wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
 
-	value = (0x50 & ~0x7F) | 16 | (1 << 6);
+	value = (0x50 & ~0x7F) | (1 << 6);
 	wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
 
 	for (i = 0; i < 4; i++) {
-- 
2.39.1

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2023-02-23 09:36:29.683013222 +0000
+++ 0036-net-txgbe-fix-default-signal-quality-value-for-KX-KX.patch	2023-02-23 09:36:28.242170234 +0000
@@ -1 +1 @@
-From 7211175417d4f6a7b03a0e7e7355dc62fced8512 Mon Sep 17 00:00:00 2001
+From 62b31a67404a62fd3e09149f17e541f7f03db80d Mon Sep 17 00:00:00 2001
@@ -5,0 +6,2 @@
+[ upstream commit 7211175417d4f6a7b03a0e7e7355dc62fced8512 ]
+
@@ -10 +11,0 @@
-Cc: stable at dpdk.org
@@ -18 +19 @@
-index 9f46d5bdb0..87935abdaa 100644
+index ce6d580636..73f3cdced1 100644
@@ -21,25 +22,25 @@
-@@ -1693,9 +1693,10 @@ txgbe_set_link_to_kx4(struct txgbe_hw *hw, bool autoneg)
- 		wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
- 	} else if (hw->fw_version <= TXGBE_FW_N_TXEQ) {
- 		value = (0x1804 & ~0x3F3F);
-+		value |= 40 << 8;
- 		wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
- 
--		value = (0x50 & ~0x7F) | 40 | (1 << 6);
-+		value = (0x50 & ~0x7F) | (1 << 6);
- 		wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
- 	}
- out:
-@@ -1907,10 +1908,10 @@ txgbe_set_link_to_kx(struct txgbe_hw *hw,
- 		value |= hw->phy.ffe_post | (1 << 6);
- 		wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
- 	} else if (hw->fw_version <= TXGBE_FW_N_TXEQ) {
--		value = (0x1804 & ~0x3F3F) | (24 << 8) | 4;
-+		value = (0x1804 & ~0x3F3F) | (40 << 8);
- 		wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
- 
--		value = (0x50 & ~0x7F) | 16 | (1 << 6);
-+		value = (0x50 & ~0x7F) | (1 << 6);
- 		wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
- 	}
- out:
+@@ -1491,9 +1491,10 @@ txgbe_set_link_to_kx4(struct txgbe_hw *hw, bool autoneg)
+ 	wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0x4F00);
+ 
+ 	value = (0x1804 & ~0x3F3F);
++	value |= 40 << 8;
+ 	wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
+ 
+-	value = (0x50 & ~0x7F) | 40 | (1 << 6);
++	value = (0x50 & ~0x7F) | (1 << 6);
+ 	wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
+ 
+ 	for (i = 0; i < 4; i++) {
+@@ -1701,10 +1702,10 @@ txgbe_set_link_to_kx(struct txgbe_hw *hw,
+ 
+ 	wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0x4F00);
+ 
+-	value = (0x1804 & ~0x3F3F) | (24 << 8) | 4;
++	value = (0x1804 & ~0x3F3F) | (24 << 8);
+ 	wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
+ 
+-	value = (0x50 & ~0x7F) | 16 | (1 << 6);
++	value = (0x50 & ~0x7F) | (1 << 6);
+ 	wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
+ 
+ 	for (i = 0; i < 4; i++) {