patch 'net/hns3: fix Rx multiple firmware reset interrupts' has been queued to stable release 22.11.3

[Xueming Li]

Hi,

FYI, your patch has been queued to stable release 22.11.3

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 06/27/23. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Queued patches are on a temporary branch at:
https://git.dpdk.org/dpdk-stable/log/?h=22.11-staging

This queued commit can be viewed at:
https://git.dpdk.org/dpdk-stable/commit/?h=22.11-staging&id=d859368e8fe219552fd2ed72ae14d492f5d283f1

Thanks.

Xueming Li <xuemingl at nvidia.com>

---
>From d859368e8fe219552fd2ed72ae14d492f5d283f1 Mon Sep 17 00:00:00 2001
From: Chengwen Feng <fengchengwen at huawei.com>
Date: Mon, 22 May 2023 21:17:39 +0800
Subject: [PATCH] net/hns3: fix Rx multiple firmware reset interrupts
Cc: Xueming Li <xuemingl at nvidia.com>

[ upstream commit e3c71325cec3353c4b9623310ece363a7c79604f ]

In the firmware (also known as IMP) reset scenario, driver interrupt
processing and firmware watchdog initialization are asynchronous.

If the driver interrupt processing is faster than firmware watchdog
initialization (that is, the driver clears the firmware reset
interrupt source before the firmware watchdog is initialized), the
driver will receive multiple firmware reset interrupts.

In the Kunpeng 920 platform, the above situation does not exist. But
it does on the newer platforms. So we add 5ms delay before drivers
clears the IMP reset interrupt source.

As for the impact of 5ms, the number of PFs managed by a firmware is
limited. Therefore, even if a DPDK process takes over all the PFs
which managed by the firmware, the delay is controllable.

Fixes: ee930d38ffca ("net/hns3: fix timing of clearing interrupt source")

Signed-off-by: Chengwen Feng <fengchengwen at huawei.com>
Signed-off-by: Dongdong Liu <liudongdong3 at huawei.com>
---
 drivers/net/hns3/hns3_ethdev.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c
index c31c6979c3..b791ec4a17 100644
--- a/drivers/net/hns3/hns3_ethdev.c
+++ b/drivers/net/hns3/hns3_ethdev.c
@@ -286,6 +286,19 @@ hns3_handle_mac_tnl(struct hns3_hw *hw)
 	}
 }
 
+static void
+hns3_delay_before_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
+{
+#define IMPRESET_WAIT_MS_TIME	5
+
+	if (event_type == HNS3_VECTOR0_EVENT_RST &&
+	    regclr & BIT(HNS3_VECTOR0_IMPRESET_INT_B) &&
+	    hw->revision >= PCI_REVISION_ID_HIP09_A) {
+		rte_delay_ms(IMPRESET_WAIT_MS_TIME);
+		hns3_dbg(hw, "wait firmware watchdog initialization completed.");
+	}
+}
+
 static void
 hns3_interrupt_handler(void *param)
 {
@@ -305,6 +318,7 @@ hns3_interrupt_handler(void *param)
 	vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 	ras_int = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 	cmdq_int = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
+	hns3_delay_before_clear_event_cause(hw, event_cause, clearval);
 	hns3_clear_event_cause(hw, event_cause, clearval);
 	/* vector 0 interrupt is shared with reset and mailbox source events. */
 	if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
-- 
2.25.1

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2023-06-25 14:31:59.651087100 +0800
+++ 0042-net-hns3-fix-Rx-multiple-firmware-reset-interrupts.patch	2023-06-25 14:31:58.355773900 +0800
@@ -1 +1 @@
-From e3c71325cec3353c4b9623310ece363a7c79604f Mon Sep 17 00:00:00 2001
+From d859368e8fe219552fd2ed72ae14d492f5d283f1 Mon Sep 17 00:00:00 2001
@@ -4,0 +5,3 @@
+Cc: Xueming Li <xuemingl at nvidia.com>
+
+[ upstream commit e3c71325cec3353c4b9623310ece363a7c79604f ]
@@ -23 +25,0 @@
-Cc: stable at dpdk.org
@@ -32 +34 @@
-index 5ef66f96c6..664226a6ef 100644
+index c31c6979c3..b791ec4a17 100644